Table of Contents
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branch instructions, 6-16
condition register logical instructions, 6-16
branch instructions, D-24
BYPASS, 38-7
cache management, 6-23
cache management instructions, D-26
CLAMP, 38-7
classes of instructions, 6-3
condition register logical, D-24
dcbf, 8-20
dcbi, 8-20
dcbst, 8-19
dcbt, 8-18
dcbtst, 8-18
dcbz, 8-19
external control, D-26
EXTEST, 38-6
floating-point
arithmetic, D-19
compare, D-20
FP load instructions, D-23
FP move instructions, D-24
FP store instructions, D-24
FPSCR isntructions, D-20
multiply-add, D-20
rounding and conversion, D-20
functional categories, D-17
HI-Z, 38-7
icbi, 8-18
illegal instructions, 6-4
instruction field conventions, lxxiv, xxii
instruction timing, 10-1
integer
arithmetic, 6-8, D-17
byte-reverse instructions, 6-13
compare, 6-9, D-18
load, D-21
load instructions, 6-12
load/store address generation, 6-11
load/store multiple instructions, 6-14
load/store string instructions, 6-14
logical, 6-10, D-18
multiple, D-22
rotate and shift, 6-10, D-18ÐD-19
store, D-22
store instructions, 6-13
isync, 8-9
load and store
byte-reverse instructions, D-22
integer multiple instructions, D-22
string instructions, D-23
load/store
byte- reverse instructions, 6-13
integer load/store address generation, 6-11
Index--6
INDEX
Integer arithmetic instructions, D-17
Integer compare instructions, D-18
Integer load instructions, D-21
Integer logical instructions, D-18
Integer multiple instructions, D-22
Integer rotate and shift instructions, D-18ÐD-19
Integer store instructions, D-22
Integer unit
Interrupt cause (ICR) register, 37-44
Interrupt controller, SIU, 11-16
Interrupts
IRQ0
IRQn (interrupt request) signals, 3-6, 13-8
MPC860 PowerQUICC UserÕs Manual
load instructions, 6-12
multiple instructions, 6-14
store instructions, 6-13
string instructions, 6-14
lwarx, 8-28
memory control, D-26
memory control (OEA), 6-23
memory control (VEA), 6-21
memory synchronization, D-23
memory synchronization (UISA), 6-17
memory synchronization (VEA), 6-20
mfspr, 8-6, 8-11
mtspr, 8-6, 8-11
optional instructions, D-38
processor control, D-25
processor control (OEA), 6-22
processor control (UISA), 6-17
processor control (VEA), 6-20
quick reference list
general information legend, D-38
sorted by form (format), D-27
sorted by function, D-17
sorted by mnemonic, D-1
sorted by opcode, D-9
reserved instructions, 6-5
SAMPLE/PRELOAD, 38-6
segment register manipulation, D-26
simplified mnemonics, 6-24
stwcx., 8-28
summary of instructions, 6-2
system linkage, 6-22, D-25
TAP instructions, 38-6
TLB management instructions, D-26
trap instructions, 6-17, D-25
UISA instructions, 6-8
overview, 4-10
SIU interrupt priority, 11-14
SIU interrupt processing, 11-15
SIU interrupt structure, 11-12
operation of IRQ0, 11-15
MOTOROLA
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