Motorola MPC860 PowerQUICC User Manual page 147

Supervisor-level registers are described in Table 5-9.
Table 5-9. MPC860-Specific Supervisor-Level SPRs
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
80 00010 10000
81 00010 10001
82 00010 10010
631 10011 10111
638 10011 11110
560 10001 10000
561 10001 10001
562 10001 10010
568 10001 11000
569 10001 11001
570 10001 11010
784 11000 10000
786 11000 10010
787 11000 10011
789 11000 10101
790 11000 10110
816 11001 10000
817 11001 10001
818 11001 10010
792 11000 11000
MOTOROLA
Name
EIE See Section 7.1.5, ÒRecoverability
after an Exception.Ó
EID
NRI
1
DPIR
IMMR Section 11.4.1, ÒInternal Memory
Map Register (IMMR).Ó
IC_CST Section 8.3.1, ÒInstruction Cache
Control RegistersÓ
IC_ADR Section 8.3.1, ÒInstruction Cache
Control RegistersÓ
IC_DAT Section 8.3.1, ÒInstruction Cache
Control RegistersÓ
DC_CST Section 8.3.2, ÒData Cache Control
RegistersÓ
DC_ADR Section 8.3.2, ÒData Cache Control
RegistersÓ
DC_DAT Section 8.3.2, ÒData Cache Control
RegistersÓ
MI_CTR Section 9.8.1, ÒIMMU Control Register
(MI_CTR)Ó
MI_AP Section 9.8.10, ÒMMU Access
Protection Registers
(MI_AP/MD_AP)Ó
MI_EPN Section 9.8.3, ÒIMMU/DMMU Effective
Page Number Register (Mx_EPN)Ó
MI_TWC Section 9.8.4, ÒIMMU Tablewalk
(MI_L1DL2P) Control Register (MI_TWC)
MI_RPN Section 9.8.6, ÒIMMU Real Page
Number Register (MI_RPN)Ó
MI_CAM Section 9.8.12.1, ÒIMMU CAM Entry
Read Register (MI_CAM)Ó
MI_RAM0 Section 9.8.12.2, ÒIMMU RAM Entry
Read Register 0 (MI_RAM0)Ó
MI_RAM1 Section 9.8.13, ÒDMMU RAM Entry
Read Register 1 (MD_RAM1)Ó
MD_CTR Section 9.8.2, ÒDMMU Control
Register (MD_CTR).Ó
Chapter 5. PowerPC Core Register Set
Part II. PowerPC Microprocessor Module
Comments
Write
Write
Write
Fetch-only
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Serialize Access
5-9