Motorola MPC860 PowerQUICC User Manual page 699

24.13.1 SCC HDLC Programming Example #1
The following initialization sequence is for an SCC HDLC channel with an external clock.
SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver
and transmitter.
1. ConÞgure the port A pins to enable TXD2 and RXD2. Set PAPAR[12,13] and clear
PADIR[12,13] and PAODR[12,13].
2. ConÞgure the port C pins to enable RTS2, CTS2, and CD2. Set PCPAR[14] clear
PCPAR[8,9] and PCDIR[8,9,14] and set PCSO[8,9].
3. ConÞgure the port A pins to enable the CLK3 pin. Set PAPAR[5] and clear
PADIR[5].
4. Connect CLK3 to SCC2 using the SI. Write 0b110 to SICR[R2CS] and
SICR[T2CS].
5. Connect the SCC2 to the NMSI (its own set of pins) and clear SICR[SC2].
6. Write 0x0001 to the SDCR to initialize the SDMA conÞguration register.
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.
8. Write 0x0041 to CPCR to execute the
This command updates RBPTR and TBPTR of the serial channel with the new
values of RBASE and TBASE.
9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.
10. Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes
(MRBLR = 0x0100) so an entire Rx frame can Þt in one buffer.
11. Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.
12. Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.
13. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.
14. Write MFLR with 0x0100 so the maximum frame size is 256 bytes.
15. Write RFTHR with 0x0001 to allow interrupts after each frame.
16. Write HMASK with 0x0000 to allow all addresses to be recognized.
17. Clear HADDR1ÐHADDR4 for clarity.
18. Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory.
RxBD[Status and Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required),
and RxBD[Buffer Pointer] = 0x0000_1000.
19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory
and contains Þve 8-bit characters. TxBD[Status and Control] = 0xBC00,
TxBD[Data Length] = 0x0005, and TxBD[Buffer Pointer] = 0x0000_2000.
20. Write 0xFFFF to SCCE to clear any previous events.
MOTOROLA
Part V. The Communications Processor Module
INIT RX AND TX PARAMS
Chapter 24. SCC HDLC Mode
command for SCC2.
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