Motorola MPC860 PowerQUICC User Manual page 891

Table 34-6. Port B Pin Assignment (Continued)
Signal
PBPAR[DDn] = 0
PB24 Port B24
PB23 Port B23
PB22 Port B22
PB21 Port B21
PB20 Port B20
PB19 Port B19
PB18 Port B18
PB17 Port B17
PB16 Port B16
PB15 Port B15
PB14 Port B14
1
Available for MPC860 Rev. B and later.
34.3.1 The Port B Registers
The four port B control registers determine whether a signal is open-drain, input or output,
and general-purpose or dedicated to a peripheral.
34.3.1.1 Port B Open-Drain Register (PBODR)
The port B open-drain register (PBODR) indicates when the port signals are conÞgured in
a normal or wired-OR conÞguration. Bits 14 and 15 of PBODR are not implemented.
PBODR is cleared by system reset.
Bit 0 1 2
Field
Reset
R/W
Addr
Bit 16 17 18
Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31
Reset 0 0 0
R/W R/W R/W R/W
Addr
Figure 34-7. Port B Open-Drain Register (PBODR)
MOTOROLA
PBPAR[DDn] = 1
PBDIR[DRn] = 0
SMRXD1
SMSYN1
SMSYN2
SMTXD2
SMRXD2
L1ST1
L1ST2
L1ST3
L1ST4
Ñ
Ñ
3 4 5 6
0000_0000_0000_0000
19 20 21 22
0 0 0 0
R/W R/W R/W R/W
Chapter 34. Parallel I/O Ports
Part V. The Communications Processor Module
Signal Function
Input to On-chip Peripherals
PBDIR[DRn] = 1
Ñ
SDACK1
SDACK2
L1CLKOB
L1CLKOA
RTS1
RTS2
1
RTS3 /L1RQb
1
RTS4 /L1RQa
BRGO3
RSTRT1
7 8 9 10
Ñ
Ñ
0xAC0
23 24 25 26
0 0 0 0
R/W R/W R/W R/W
0xAC2
(Default)
SMRXD1 = GND
SMSYN1 = GND
SMSYN2 = GND
Ñ
SMRXD2 = GND
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
11 12 13 14
27 28 29 30
0 0 0 0
R/W R/W R/W R/W
15
31
0
R/W
34-9