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30.4.13 SMC Transparent TSA Programming Example
The following is an example initialization sequence for the SMC1 transparent channel over
the TSA. It is assumed that the TSA and the TDM pins have been set up to route time-slot
data to the SMC transmitter and receiver. Chapter 21, ÒSerial Interface,Ó has examples for
conÞguring the TSA which provides transmit and receive clocks and synchronization
signals internally.
1. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port
RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008.
2. Program CPCR to execute the
0x0091 to the CPCR.
3. Initialize the SDCR to 0x0001.
4. Write RFCR and TFCR with 0x10 for normal operation.
5. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16
bytes, so MRBLR = 0x0010.
6. Initialize the RxBD and assume the Rx buffer is at 0x0000_1000 in main memory.
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].
7. Initialize the TxBD and assume the Tx buffer is at 0x0000_2000 in main memory
and contains Þve 8-bit characters. Write 0xB000 to TxBD[Status and Control],
0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].
8. Write 0xFF to SMCE to clear any previous events.
9. Write 0x13 to SMCM to enable all possible SMC interrupts.
10. Write 0x0000_0010 to the CIMR so SMC1 can generate a system interrupt.
Initialize CICR.
11. Set SMCMR to 0x3830 for 8-bit characters, unreversed data, and normal operation
(not loopback). The transmitter and receiver are not enabled yet.
12. Write 0x3833 to SMCMR to enable the SMC transmitter and receiver. This
additional write ensures that TEN and REN are enabled last.
30.5 SMC in GCI Mode
A single SMC can control both the C/I and monitor channels of a GCI frame. When using
the SCIT conÞguration of GCI, one SMC can handle SCIT channel 0 and the other can
handle SCIT channel 1. The main features of the SMC in GCI mode are as follows:
¥ Each SMC channel can support both the C/I and monitor channels of the GCI
(IOM-2) in ISDN applications
¥ Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1
¥ Full-duplex operation
¥ Local loopback and echo capability for testing
MOTOROLA
INIT TX AND RX PARAMETERS
Chapter 30. Serial Management Controllers
Part V. The Communications Processor Module
command. Write
30-31
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