Motorola MPC860 PowerQUICC User Manual page 200

Part II. PowerPC Microprocessor Module
provide the index to select a cache set. Bits A[28Ð31] select a byte within a block. The tags
consist of the high-order physical address bits PA[0Ð20]. Address translation occurs in
parallel with set selection (from A[21Ð27]).
The two state bits implement a three-state (modiÞed-valid/unmodiÞed-valid/invalid)
protocol. The MPC860 does not provide support for snooping external bus activity. All
coherency between the internal caches and external agents (memory or I/O devices) must
be controlled by software.
The data cache also implements a lock bit for each cache block that allows data to be loaded
into the data cache and locked. The MPC860 supports commands for locking and unlocking
individual cache blocks and for unlocking all the cache blocks at once.
8.3 Cache Control Registers
The MPC860Õs caches are controlled by programming commands using the cache control
registers and by issuing dedicated PowerPC cache control instructions. This section
describes control of the instruction and data caches by the cache control registers.
Section 8.4, ÒPowerPC Cache Control Instructions,Ó describes the PowerPC cache control
instructions.
8.3.1 Instruction Cache Control Registers
The MPC860 implements three special purpose registers (SPRs) to control the instruction
cacheÑthe instruction cache control and status register (IC_CST), the instruction cache
address register (IC_ADR), and the instruction cache data port register (IC_DAT). The
instruction cache can be disabled, invalidated, or locked by issuing the appropriate
commands to the instruction cache control registers (IC_CST, IC_ADR, and IC_DAT). In
addition, the instruction cache control registers can be used to read the contents and tags of
speciÞc instruction cache blocks.
The mtspr and mfspr instructions are used to access the cache control registers, but they
can be accessed only by supervisor-level programs (that is, when MSR[PR] = 0). Any
attempt to access these SPRs with a user-level program (MSR[PR] = 1) results in a
supervisor-level program exception.
The IC_CST register, shown in Figure 8-3, has an SPR encoding of 560.
8-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA