Motorola MPC860 PowerQUICC User Manual page 726

Part V. The Communications Processor Module
Table 26-11. Asynchronous HDLC TxBD Status and Control Field Descriptions (Con-
Bits Name
6 CM Continuous mode.
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing its buffer to be resent when the CP next
accesses this BD. However, R is cleared if an error occurs during transmission, regardless of CM.
7Ð14 Ñ Reserved, should be cleared.
15 CT CTS lost. In NMSI mode, CTS is lost during frame transmission. If more than one buffer has data in the
FIFO when this error occurs, CT is set in the currently open TxBD. Written by the asynchronous HDLC
controller after it Þnishes sending the buffer.
The data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer
Descriptors (BDs).Ó
26.16 Differences between HDLC and Asynchronous
HDLC
The basic differences between HDLC and asynchronous HDLC modes are as follows:
¥ Asynchronous HDLC does not support the
¥ Because asynchronous HDLC has no maximum received frame length counter, it
receives all characters between opening and closing ßags. There is no way to keep
it from writing to memory. This does not affect the number of bytes received into a
speciÞc BD. A frame over the maximum length is received into memory in its
entirety.
¥ If an error causes a frame to stop being received, the character being received at the
moment the error occurred is not written into memory. For example, if a CD lost
error occurs, the frame is closed and the partial character is not written to memory.
Thus, the octet count reßects only the number of bytes written to memory.
¥ The automatic error counters in the HDLC controller are not implemented in the
asynchronous HDLC controller.
¥ Noisy characters (characters for which all three samples are not identical) are not
accounted for in the asynchronous HDLC controller. It is assumed that the CRC
catches any data integrity problems.
26.17 SCC Asynchronous HDLC Programming
Example
The following example shows initialization for an SCC in asynchronous HDLC mode.
1. Initialize SDCR.
2. In NMSI mode, conÞgure ports A and C to enable RXD, TXD, CTS, CD, and RTS.
In other modes, conÞgure the TSA and its pins.
3. ConÞgure a baud rate generator to the appropriate channel clocking frequency.
26-14
Description
MPC860 PowerQUICC UserÕs Manual
GRACEFUL STOP TRANSMIT
command.
MOTOROLA