Motorola MPC860 PowerQUICC User Manual page 306

Part III. Configuration
Table 11-24 describes PISCR Þelds.
Bits Name
0Ð7 PIRQ Periodic interrupt request level. ConÞgures internal interrupt levels for periodic interrupts.
Figure 11-7 shows interrupt request levels.
8 PS Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect).
0 The PIT is unaffected.
1 The PIT has issued an interrupt.
9Ð12 Ñ Reserved, should be cleared.
13 PIE Periodic interrupt enable
0 Disables the PS bit.
1 Enables the PS bit to generate an interrupt.
14 PITF PIT freeze enable
0 The PIT is unaffected by the FRZ signal.
1 The FRZ signal stops the PIT.
15 PTE Periodic timer enable
0 The PIT is disabled.
1 The PIT is enabled.
11.11.2 PIT Count Register (PITC)
PITC contains a 16-bit value to be loaded into the periodic interrupt down counter. Note
that PITC is a keyed register. It must be unlocked in PITCK before it can be written.
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17 18
Field
Reset
R/W
Addr
Table 11-25 describes PITC Þelds.
Bits Name
0Ð15 PITC PIT count. Contains the count for the periodic timer. Setting this Þeld to 0xFFFF selects the maximum
count period.
11-32
Table 11-24. PISCR Field Descriptions
2 3 4 5 6
(IMMR & 0xFFFF0000) + 0x244
19 20 21 22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x246
Figure 11-30. PIT Count Register (PITC)
Table 11-25. PITC Field Descriptions
MPC860 PowerQUICC UserÕs Manual
Description
7 8 9 10 11
PITC
Ñ
R/W
23 24 25 26 27
Ñ
R/W
Description
12 13 14 15
28 29 30 31
MOTOROLA