Motorola MPC860 PowerQUICC User Manual page 905

35.2 CPM Interrupt Source Priorities
The CPIC has 29 interrupt sources that assert a single programmable interrupt request level
to the core. Default interrupt priorities are as shown in Table .
Table 35-1. Prioritization of CPM Interrupt Sources
Priority Source Description
0x1F Parallel I/OÐPC15
(Highest)
2
0x1E SCCa (grouped and spread)
2
0x1D SCCb (grouped)
2
0x1C SCCc (grouped)
2
0x1B SCCd (grouped)
0x1A Parallel I/OÐPC14
0x19 Timer 1
0x18 Parallel I/OÐPC13
0x17 Parallel I/OÐPC12
0x16 SDMA channel bus error
0x15 IDMA1
0x14 IDMA2
2
0x13 SCCb (spread)
0x12 Timer 2
0x11 RISC timer table
2
0x10 I C
1
Port C interrupts (external sources) are described in Section 34.4.1.5, ÒPort C Interrupt Control Register
(PCINT).Ó
2
SCCs can be programmed to any of these locations. Group and spread are described in Section 35.2.1,
ÒProgramming Relative Priority (Grouping and Spreading).Ó
The only true SDMA interrupt source is the SDMA channel bus error entry that is reported
when a bus error occurs during an SDMA access. Other SDMA-related interrupts are
reported through each individual SCC, SMC, SPI, or I
reprioritized as described in the next two sections.
35.2.1 Programming Relative Priority (Grouping and Spreading)
The relative priority between the SCCs is programmable dynamically through
CICR[SCnP], shown in Table 35-3. Table 35-1 has no explicit entry for SCCs because the
entries can be mapped to any of these locations. This is programmed in the CICR (see
Table 35-3).
MOTOROLA
Multiple
Events
1
No
Yes
Yes
Yes
Yes
1
No
Yes
1
No
1
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Chapter 35. CPM Interrupt Controller
Part V. The Communications Processor Module
Priority Source Description
0x0F Parallel I/OÐPC11
0x0E Parallel I/OÐPC10
2
0x0D SCCc (spread)
0x0C Timer3
0x0B Parallel I/OÐPC9
0x0A Parallel I/OÐPC8
0x09 Parallel I/OÐPC7
2
0x08 SCCd (spread)
0x07 Timer4
0x06 Parallel I/OÐPC6
0x05 SPI
0x04 SMC1
0x03 SMC2/PIP
0x02 Parallel I/OÐPC5
0x01 Parallel I/OÐPC4
0x00 Reserved
(Lowest)
2
C channel. SCCs interrupts can be
Multiple
Events
1
No
1
No
Yes
Yes
1
No
1
No
1
No
Yes
Yes
1
No
Yes
Yes
Yes
1
No
1
No
Ñ
35-3