Motorola MPC860 PowerQUICC User Manual page 1028

Appendixes
Table C-5. MPC860-Specific Supervisor-Level SPRs (Continued)
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
793 11000 11001
794 11000 11010
795 11000 11011
796 11000 11100
797 11000 11101
798 11000 11110
799 11000 11111
824 11001 11000
825 11001 11001
826 11001 11010
1
Fetch-only register; mtspr is ignored; using mfspr gives an undeÞned value.
Debug-level registers are described in Table C-6. These registers are described in
Section 37.5.1, ÒDevelopment Support Registers.Ó
Table C-6. MPC860-Specific Debug-Level SPRs
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
144 00100 10000
145 00100 10001
146 00100 10010
147 00100 10011
148 00100 10100
149 00100 10101
150 00100 10110
151 00100 10111
C-4
Name
M_CASID Section 9.8.9, ÒMMU Current Address
Space ID Register (M_CASID)Ó
MD_AP Section 9.8.10, ÒMMU Access
Protection Registers
(MI_AP/MD_AP)Ó
MD_EPN Section 9.8.3, ÒIMMU/DMMU Effective
Page Number Register (Mx_EPN)Ó
M_TWB Section 9.8.8, ÒMMU Tablewalk Base
(MD_L1P) Register (M_TWB)Ó
MD_TWC Section 9.8.5, ÒDMMU Tablewalk
(MD_L1DL2P) Control Register (MD_TWC)Ó
MD_RPN Section 9.8.7, ÒDMMU Real Page
Number Register (MD_RPN)Ó
M_TW (M_SAVE) Section 9.8.11, ÒMMU Tablewalk
Special Register (M_TW)Ó
MD_CAM Section 9.8.12.4, ÒDMMU CAM Entry
Read Register (MD_CAM)Ó
MD_RAM0 Section 9.8.12.5, ÒDMMU RAM Entry
Read Register 0 (MD_RAM0)Ó
MD_RAM1 Section 9.8.13, ÒDMMU RAM Entry
Read Register 1 (MD_RAM1)Ó
Name
CMPA
CMPB
CMPC
CMPD
ICR
DER
COUNTA
COUNTB
MPC860 PowerQUICC UserÕs Manual
Comments
Serialize Access
Fetch sync on write
Fetch sync on write
Fetch sync on write
Fetch sync on write
Fetch sync on write
Fetch sync on write
Fetch sync on write
Fetch sync on write
Serialize Access
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
Write (as a store)
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