Motorola MPC860 PowerQUICC User Manual page 460

Part IV. Hardware Interface
The state of the external signals may change (if speciÞed in the RAM array) at any edge of
GCLK1_50 and GCLK2_50, plus a propagation delay, speciÞed in the MPC860 Hardware
SpeciÞcations. Note however that only the CS signal corresponding to the currently
accessed bank will be manipulated by the UPM pattern when it runs. The BS signal
assertion and negation timing is also speciÞed for each cycle in the RAM word, but which
of the four BS signals will be manipulated by the being run depends on the port size of the
speciÞed bank, the external address accessed, and the value of TSIZn. The GPL lines toggle
as programmed for any access that initiates a particular pattern, but resolution of control is
slightly more limited.
The examples in Figure 16-36 and Figure 16-37 show how to control the timing of CS,
GPL1, and GPL2. UPM RAM words determine the values of the CST[1Ð4], G1T3, G1T4,
G2T3, and G2T4 bits, which specify the timing of chip-selects, byte-selects, and GPL
signals based on the edges of GCLK1_50 or GCLK2_50. The clock phases shown refer to
the timing windows when the signals controlled by these bits in the RAM word are driven.
Internal
System Clock
CLKOUT
GCLK1_50
GCLK2_50
CS CST4
GPL1
GPL2
Clock Phase
Figure 16-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00)
16-34
CST1 CST2
G1T4
G2T4
1 2 3
RAM Word 1
MPC860 PowerQUICC UserÕs Manual
CST3 CST4 CST1
G1T3 G1T4
G2T3 G2T4
4 1 2
RAM Word 2
CST2 CST3
G1T4 G1T3
G1T4 G2T3
3 4
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