Motorola MPC860 PowerQUICC User Manual page 967

Result: An event is correctly detected if the compiler chooses a load/store instruction
with data size of half-word. If the compiler chooses load/store instructions with data
size greater than half-word (word, multiple), false detections may occur.
¥ These can only be ignored by the software that handles the breakpoints. Figure 37-4
shows this partially supported scenario:
Possible false detect on these half-words when using word/multiple
Figure 37-4. Partially Supported Watchpoints/Breakpoint Example
37.2.4.3 Context Dependent Filter
The core can be programmed to recognize only internal breakpoints when MSR[RI] = 1
(maskable mode) or to always recognize internal breakpoints (nonmaskable mode).
In maskable mode, when the core is programmed only to recognize internal breakpoints
(when MSR[RI] =1), it is possible to debug all parts of the code, except when SRR0 and
SRR1, DAR, and DSISR are busy as indicated by MSR[RI] = 0 (in the prologues and
epilogues of exception handlers). Internal breakpoints detected when MSR[RI] = 0 are lost
and debug counters do not count detected watchpoints. Detected watchpoints are always
reported on the external pins, regardless of the value of MSR[RI].
In nonmaskable mode, when the core is programmed to recognize internal breakpoints, all
parts of the code can be debugged. However, if an internal breakpoint is recognized when
MSR[RI] = 0 (SRR0 and SRR1 are busy), the machine enters a nonrestartable state. See
Section 7.1.5, ÒRecoverability after an Exception.Ó
The core defaults to maskable mode after reset. The core is put in nonmaskable mode by
setting LCTRL2[BRKNOMSK], which controls all internal I- and L-breakpoints. See
Section 37.5.1.5, ÒLoad/Store Support AND-OR Control Register (LCTRL2).Ó
37.2.4.4 Ignore First Match
The ignore Þrst match bit, ICTRL[IFM], facilitates the debuggerÕs ÒcontinueÓ and Ògo from
xÓ utilities for instruction breakpoints. When an instruction breakpoint is Þrst enabled, the
Þrst instruction cannot cause an instruction breakpoint if ICTRL[IFM] = 1. This is used for
ÒcontinueÓ utilities. If IFM = 0, every matched instruction causes an instruction breakpoint.
This is used for Ògo from xÓ. IFM is set by software and cleared by hardware; after the Þrst
instruction breakpoint, the match is ignored. Load/store breakpoints and all
counter-generated breakpoints (instruction and load/store) are unaffected by this mode.
MOTOROLA
0x00000000
0x00000004
0x00000008
0x0000000c
0x00000010
Chapter 37. System Development and Debugging
Part VI. Debug and Test
37-17