Motorola MPC860 PowerQUICC User Manual page 900

Part V. The Communications Processor Module
are cleared at system reset, which conÞgures all port D signals as general-purpose inputs.
Table describes port D signal defaults.
Signal
PDPAR[DDn] = 0
PD15 PORT D15
PD14 PORT D14
PD13 PORT D13
PD12 PORT D12
PD11 PORT D11
PD10 PORT D10
PD9 PORT D9
PD8 PORT D8
PD7 PORT D7
PD6 PORT D6
PD5 PORT D5
PD4 PORT D4
PD3 PORT D3
Specialized versions of the MPC860 multiplex the port D signals with other functions, such
as an ATM UTOPIA interface or 100BASE-T MII (media-independent interface). See the
speciÞc partÕs supplementary documentation for details.
34.5.1 Port D Registers
Port D has three memory-mapped, read/write control registers.
34.5.1.1 Port D Data Register
A read of the port D data (PDDAT) register returns the value of the signal, regardless of
whether it is an input or output. This allows output conßicts to be found on the signal by
comparing the written data with the data on the signal. A write to a PDDAT bit is latched,
and if conÞgured as an output, is driven onto its respective signal. PDDAT can be read or
written at any time. PDDAT is not initialized and is undeÞned by reset.
34-18
Table 34-17. Port D Pin Assignment
Pin Function
PDPAR[DDn] = 1
L1TSYNCA
L1RSYNCA
L1TSYNCB
L1RSYNCB
RXD3
TXD3
RXD4
TXD4
RTS3
RTS4
REJECT2
REJECT3
REJECT4
MPC860 PowerQUICC UserÕs Manual
Input to On-Chip Peripherals
(Default)
L1TSYNCA = GND
L1RSYNCA = GND
L1TSYNCB = GND
L1RSYNCB = GND
RXD3 = PA11 (RXD3)
Ñ
RXD4 = PA9 (RXD4)
Ñ
Ñ
Ñ
REJECT2 = VDD
REJECT3 = VDD
REJECT4 = VDD
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