Motorola MPC860 PowerQUICC User Manual page 855

Bit 0
Field STR
Reset
R/W
Addr
Figure 32-10. I
Table 32-5 describes I2COM Þelds.
Bits Name
0 STR Start transmit. In master mode, setting STR causes the I
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I
load the Tx data register from the current Tx buffer (if ready) and start sending when it receives an
address byte that matches the slave address with R/W = 1. STR is always read as a 0.
1Ð6 Ñ Reserved and should be cleared.
7 M/S Master/slave. ConÞgures the I
2
0 I C is a slave.
2
1 I C is a master.
32.5 I C Parameter RAM
2
The I 2 C controller parameter RAM area, shown in Table 32-6, is used for the general I
parameters. It is similar to the SCC general-purpose parameter RAM. Certain parameter
RAM values, such as the maximum receive buffer length (MRBLR), must be initialized by
the user before the I
initialization. Software usually does not access parameter RAM entries once they are
initialized; they should be changed only when the I
1
Offset Name Width
0x00 RBASE Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.
0x02 TBASE Hword
0x04 RFCR Byte
0x05 TFCR Byte
MOTOROLA
1 2
2
C Command Register (I2COM)
Table 32-5. I2COM Field Descriptions
2
C controller to operate as a master or a slave.
2
C is enabled, while other parameters, used by the CPM, do not need
2
Table 32-6. I C Parameter RAM Memory Map
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
allocated for the Tx and Rx sections of the I
2
the I C. Furthermore, do not conÞgure BD tables of the I
controllerÕs parameter RAM.
RBASE and TBASE should be divisible by eight.
Rx/Tx function code. Contains the value to appear on AT[1Ð3] when the associated
SDMA channel accesses memory. Also controls the byte-ordering convention for
transfers. See Figure 32-11 and Table 32-7.
Chapter 32. I2C Controller
Part V. The Communications Processor Module
3 4
Ñ
0000_0000
R/W
0x86C
Description
2
C controller to start sending data from the
2
C is inactive.
Description
2
C. Initialize RBASE/TBASE before enabling
5 6
M/S
2
C controller is idle causes it to
2
C to overlap any other active
7
2 C
32-9