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¥ Memory synchronization instructionsÑThese instructions are used for memory
synchronizing. See Sections 6.2.4.6 and 6.2.5.2 for more information.
¥ Memory control instructionsÑThese instructions provide control of caches, and
TLBs. For more information, see Sections 6.2.5.3 and 6.2.6.3.
¥ System linkage instructionsÑFor more information, see Section 6.2.6.1, ÒSystem
Linkage Instructions.Ó
Note that this grouping of instructions does not necessarily indicate the execution unit that
processes a particular instruction or group of instructions. This information, which is useful
in taking full advantage of the MPC860Õs parallel instruction execution, is provided in
Chapter 8, ÒInstruction Set,Ó in The Programming Environments Manual.
Integer instructions operate on word operands. The PowerPC architecture uses instructions
that are four bytes long and word-aligned. It provides for byte, half word, and word operand
loads and stores between memory and a set of 32 general-purpose registers (GPRs).
Arithmetic and logical instructions do not read or modify memory. To use the contents of a
memory location in a computation and then modify the same or another memory location,
the memory contents must be loaded into a register, modiÞed, and then written to the target
location using load and store instructions.
The description of each instruction includes the mnemonic and a formatted list of operands.
To simplify assembly language programming, a set of simpliÞed mnemonics (extended
mnemonics in the architecture speciÞcation) and symbols is provided for some of the
frequently-used instructions; see Appendix F, ÒSimpliÞed Mnemonics,Ó in The
Programming Environments Manual for a complete list of simpliÞed mnemonic examples.
6.2.1 Classes of Instructions
The MPC860 instructions belong to one of the following three classes:
¥ Defined
¥ Illegal
¥ Reserved
Note that while the deÞnitions of these terms are consistent among the PowerPC
processors, the assignment of these classiÞcations is not. For example, an instruction that
is speciÞc to 64-bit implementations is considered deÞned for 64-bit implementations but
illegal for 32-bit implementations such as the MPC860.
The class is determined by examining the primary opcode and the extended opcode, if any.
If the opcode, or combination of opcode and extended opcode, is not that of a deÞned
instruction or of a reserved instruction, the instruction is illegal.
In future versions of the PowerPC architecture, instruction codings that are now illegal may
become assigned to instructions in the architecture, or may be reserved by being assigned
to processor-speciÞc instructions.
MOTOROLA
Chapter 6. MPC860 Instruction Set
Part II. PowerPC Microprocessor Module
6-3
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