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Part V. The Communications Processor Module
34.1 Features
The following lists the main features of the parallel I/O ports:
¥ Port A is 16 bits
¥ Port B is 18 bits. Port B is shared with the PIP, which is described in Chapter 33,
ÒParallel Interface Port.Ó
¥ Port C is 12 bits
¥ Port D is 13 bits
¥ All ports are bidirectional
¥ All ports are three-stated at hardware reset
¥ All ports have alternate on-chip peripheral functions and all signal values can be
read while the signal is connected to an on-chip peripheral
¥ Ports A and B have open-drain capability
¥ Port C has 12 interrupt input signals
34.2 Port A
Port A signals are conÞgured as follows in the port A pin assignment register (PAPAR):
¥ General-purpose I/O signal (the corresponding PAPAR[DDn] = 0)
¥ Dedicated on-chip peripheral signal (PAPAR[DDn] = 1)
PAPAR and the port A data direction register (PADIR) are cleared at reset, thus conÞguring
all port A signals as general-purpose input signals. Table shows defaults for port A signal
options.
Signal
PAPAR[DDn] = 0
(General I/O)
PA15
PORT A15
PA14
PORT A14
PA13
PORT A13
PA12
PORT A12
PA11
PORT A11
PA10
PORT A10
PA9
PORT A9
PA8
PORT A8
PA7
PORT A7
34-2
Table 34-1. Port A Pin Assignment
PAPAR[DDn] = 1
1
PADIR[DRn] = 0
RXD1
TXD1
RXD2
TXD2
3
RXD3
3
TXD3
3
RXD4
3
TXD4
CLK1/TIN1/L1RCLKA
MPC860 PowerQUICC UserÕs Manual
Pin Function
Input to On-Chip Peripherals
PADIR[DRn] = 1
2
RXD4
2
TXD4
Ñ
Ñ
L1TXDB
L1RXDB
L1TXDA
L1RXDA
4
BRGO1
CLK1/TIN1/L1RCLKA = BRGO1
(Default)
GND
Ñ
GND
Ñ
UndeÞned
GND
UndeÞned
L1RXDA = GND
MOTOROLA
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