Motorola ColdFire MCF5282 Manuals

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Motorola ColdFire MCF5282 User Manual

Motorola ColdFire MCF5282 User Manual (816 pages)

Motorola Microcontroller User's Manual  
Brand: Motorola | Category: Microcontrollers | Size: 9.86 MB
Table of contents
Table Of Contents5................................................................................................................................................................
About This Book43................................................................................................................................................................
Suggested Reading46................................................................................................................................................................
General Information46................................................................................................................................................................
Acronyms And Abbreviations48................................................................................................................................................................
Revision History52................................................................................................................................................................
Overview57................................................................................................................................................................
Mcf5282 Key Features57................................................................................................................................................................
Mcf5282 Block Diagram63................................................................................................................................................................
Version 2 Coldfire Core64................................................................................................................................................................
Cache Configuration64................................................................................................................................................................
System Control Module66................................................................................................................................................................
External Interface Module (eim)66................................................................................................................................................................
Chip Select67................................................................................................................................................................
Power Management67................................................................................................................................................................
General Input/output Ports67................................................................................................................................................................
Interrupt Controllers (intc0/intc1)67................................................................................................................................................................
Sdram Controller67................................................................................................................................................................
Test Access Port68................................................................................................................................................................
Uart Modules68................................................................................................................................................................
Dma Timers (dtim0-dtim3)69................................................................................................................................................................
General-purpose Timers (gpta/gptb)69................................................................................................................................................................
Periodic Interrupt Timers (pit0-pit3)69................................................................................................................................................................
Software Watchdog Timer70................................................................................................................................................................
Phase Locked Loop (pll)70................................................................................................................................................................
Dma Controller70................................................................................................................................................................
Reset70................................................................................................................................................................
Mcf5282-specific Features71................................................................................................................................................................
Fast Ethernet Controller (fec)71................................................................................................................................................................
Flexcan71................................................................................................................................................................
I 2 C Bus71................................................................................................................................................................
Queued Serial Peripheral Interface (qspi)71................................................................................................................................................................
Queued Analog-to-digital Converter (qadc)71................................................................................................................................................................
Coldfire Core73................................................................................................................................................................
Processor Pipelines73................................................................................................................................................................
Coldfire Processor Core Pipelines73................................................................................................................................................................
Processor Register Description74................................................................................................................................................................
User Programming Model74................................................................................................................................................................
Condition Code Register (ccr)76................................................................................................................................................................
Ccr Field Descriptions76................................................................................................................................................................
Emac Programming Model77................................................................................................................................................................
Supervisor Programming Model77................................................................................................................................................................
Emac Register Set77................................................................................................................................................................
Status Register78................................................................................................................................................................
Sr Field Descriptions78................................................................................................................................................................
Programming Model80................................................................................................................................................................
Coldfire Cpu Registers80................................................................................................................................................................
Additions To The Instruction Set Architecture81................................................................................................................................................................
Exception Processing Overview82................................................................................................................................................................
Isa Revision A+ New Instructions82................................................................................................................................................................
Exception Vector Assignments83................................................................................................................................................................
Exception Stack Frame Definition84................................................................................................................................................................
Exception Stack Frame Form84................................................................................................................................................................
Format Field Encodings84................................................................................................................................................................
Processor Exceptions85................................................................................................................................................................
Access Error Exception85................................................................................................................................................................
Fault Status Encodings85................................................................................................................................................................
Address Error Exception86................................................................................................................................................................
Illegal Instruction Exception86................................................................................................................................................................
Divide-by-zero86................................................................................................................................................................
Privilege Violation86................................................................................................................................................................
Trace Exception86................................................................................................................................................................
Unimplemented Line-a Opcode87................................................................................................................................................................
Unimplemented Line-f Opcode87................................................................................................................................................................
Debug Interrupt87................................................................................................................................................................
Rte And Format Error Exception88................................................................................................................................................................
Trap Instruction Exception88................................................................................................................................................................
Interrupt Exception88................................................................................................................................................................
Fault-on-fault Halt88................................................................................................................................................................
Reset Exception88................................................................................................................................................................
D0 Hardware Configuration Info89................................................................................................................................................................
D0 Hardware Configuration Info Field Description90................................................................................................................................................................
D1 Hardware Configuration Info91................................................................................................................................................................
Instruction Execution Timing93................................................................................................................................................................
Timing Assumptions93................................................................................................................................................................
Move Instruction Execution Times94................................................................................................................................................................
Misaligned Operand References94................................................................................................................................................................
Move Byte And Word Execution Times95................................................................................................................................................................
Move Long Execution Times95................................................................................................................................................................
Standard One Operand Instruction Execution Times96................................................................................................................................................................
Standard Two Operand Instruction Execution Times96................................................................................................................................................................
Miscellaneous Instruction Execution Times98................................................................................................................................................................
Emac Instruction Execution Times99................................................................................................................................................................
Branch Instruction Execution Times100................................................................................................................................................................
Coldfire Instruction Set Architecture Enhancements100................................................................................................................................................................
General Branch Instruction Execution Times100................................................................................................................................................................
Bra, Bcc Instruction Execution Times100................................................................................................................................................................
Enhanced Multiply-accumulate Unit (emac)105................................................................................................................................................................
Multiply-accumulate Unit105................................................................................................................................................................
Introduction To The Mac106................................................................................................................................................................
Multiply-accumulate Functionality Diagram106................................................................................................................................................................
General Operation107................................................................................................................................................................
Infinite Impulse Response (iir) Filter107................................................................................................................................................................
Four-tap Fir Filter107................................................................................................................................................................
Fractional Alignment108................................................................................................................................................................
Signed And Unsigned Integer Alignment108................................................................................................................................................................
Memory Map/register Set110................................................................................................................................................................
Mac Status Register (macsr)110................................................................................................................................................................
Macsr Field Descriptions111................................................................................................................................................................
Summary Of S/u, F/i, And R/t Control Bits112................................................................................................................................................................
Mask Register (mask)114................................................................................................................................................................
Emac Instruction Set Summary116................................................................................................................................................................
Emac Instruction Summary116................................................................................................................................................................
Data Representation117................................................................................................................................................................
Emac-specific Oep Sequence Stall117................................................................................................................................................................
Mac Opcodes118................................................................................................................................................................
Two's Complement, Signed Fractional Equation118................................................................................................................................................................
Cache Features125................................................................................................................................................................
Cache Physical Organization125................................................................................................................................................................
Cache Operation127................................................................................................................................................................
Interaction With Other Modules127................................................................................................................................................................
Cache Block Diagram127................................................................................................................................................................
Memory Reference Attributes128................................................................................................................................................................
Cache Coherency And Invalidation128................................................................................................................................................................
Cache Miss Fetch Algorithm/line Fills129................................................................................................................................................................
Initial Fetch Offset Vs. Clnf Bits129................................................................................................................................................................
Instruction Cache Operation As Defined By Cacr[31, 10]130................................................................................................................................................................
Cache Programming Model131................................................................................................................................................................
Cache Registers Memory Map131................................................................................................................................................................
Cache Registers131................................................................................................................................................................
Cache Control Register (cacr)132................................................................................................................................................................
Cacr Field Descriptions132................................................................................................................................................................
Cache Configuration As Defined By Cacr[31, 23, 22]134................................................................................................................................................................
Cache Invalidate All As Defined By Cacr[23, 22, 21, 20]134................................................................................................................................................................
Access Control Registers (acr0, Acr1)135................................................................................................................................................................
External Fetch Size Based On Miss Address And Clnf135................................................................................................................................................................
Acr Field Descriptions135................................................................................................................................................................
Static Ram (sram)137................................................................................................................................................................
Sram Features137................................................................................................................................................................
Sram Operation137................................................................................................................................................................
Sram Programming Model137................................................................................................................................................................
Sram Base Address Register (rambar)138................................................................................................................................................................
Sram Initialization139................................................................................................................................................................
Sram Initialization Code140................................................................................................................................................................
Typical Rambar Setting Examples140................................................................................................................................................................
Coldfire Flash Module (cfm)143................................................................................................................................................................
Features143................................................................................................................................................................
Block Diagram144................................................................................................................................................................
Cfm Block Diagram145................................................................................................................................................................
Memory Map146................................................................................................................................................................
Cfm Array Memory Map146................................................................................................................................................................
Cfm Configuration Field147................................................................................................................................................................
Flash Base Address Register (flashbar)147................................................................................................................................................................
Flashbar Field Descriptions149................................................................................................................................................................
Cfm Registers150................................................................................................................................................................
Register Descriptions150................................................................................................................................................................
Cfm Module Configuration Register (cfmcr)150................................................................................................................................................................
Cfm Register Address Map150................................................................................................................................................................
Cfm Clock Divider Register (cfmclkd)151................................................................................................................................................................
Cfmcr Field Descriptions151................................................................................................................................................................
Cfm Security Register (cfmsec)152................................................................................................................................................................
Cfmclkd Field Descriptions152................................................................................................................................................................
Cfmsec Field Descriptions153................................................................................................................................................................
Cfm Protection Register (cfmprot)154................................................................................................................................................................
Cfmprot Field Descriptions154................................................................................................................................................................
Cfmprot Protection Diagram155................................................................................................................................................................
Cfm Supervisor Access Register (cfmsacc)155................................................................................................................................................................
Cfm Data Access Register (cfmdacc)156................................................................................................................................................................
Cfmsacc Field Descriptions156................................................................................................................................................................
Cfmdacc Field Descriptions156................................................................................................................................................................
Cfm User Status Register (cfmustat)157................................................................................................................................................................
Cfmustat Field Descriptions157................................................................................................................................................................
Cfm Command Register (cfmcmd)158................................................................................................................................................................
Cfmcmd Field Descriptions158................................................................................................................................................................
Cfmcmd User Mode Commands158................................................................................................................................................................
Cfm Operation159................................................................................................................................................................
Read Operations159................................................................................................................................................................
Write Operations159................................................................................................................................................................
Program And Erase Operations159................................................................................................................................................................
Flash User Commands162................................................................................................................................................................
Example Program Algorithm163................................................................................................................................................................
Stop Mode164................................................................................................................................................................
Master Mode165................................................................................................................................................................
Flash Security Operation165................................................................................................................................................................
Back Door Access166................................................................................................................................................................
Erase Verify Check166................................................................................................................................................................
Interrupts167................................................................................................................................................................
Cfm Interrupt Sources167................................................................................................................................................................
Memory Map And Registers169................................................................................................................................................................
Low-power Interrupt Control Register (lpicr)171................................................................................................................................................................
Lpicr Field Description171................................................................................................................................................................
Low-power Control Register (lpcr)172................................................................................................................................................................
Xlpm_ipl Settings172................................................................................................................................................................
Lpcr Field Descriptions172................................................................................................................................................................
Functional Description173................................................................................................................................................................
Low-power Modes173................................................................................................................................................................
Pll/clkout Stop Mode Operation173................................................................................................................................................................
Wait Mode174................................................................................................................................................................
Peripheral Behavior In Low-power Modes175................................................................................................................................................................
Reset Controller178................................................................................................................................................................
Clock Module179................................................................................................................................................................
Watchdog Timer180................................................................................................................................................................
Summary Of Peripheral State During Low-power Modes184................................................................................................................................................................
Cpu And Peripherals In Low-power Modes184................................................................................................................................................................
System Control Module (scm)187................................................................................................................................................................
Memory Map And Register Definition188................................................................................................................................................................
Scm Register Map188................................................................................................................................................................
Internal Peripheral System Base Address Register (ipsbar)189................................................................................................................................................................
Memory Base Address Register (rambar)190................................................................................................................................................................
Ips Base Address Register (ipsbar)190................................................................................................................................................................
Ipsbar Field Description190................................................................................................................................................................
Rambar Field Description191................................................................................................................................................................
Core Reset Status Register (crsr)192................................................................................................................................................................
Core Watchdog Control Register (cwcr)192................................................................................................................................................................
Crsr Field Descriptions192................................................................................................................................................................
Cwcr Field Description194................................................................................................................................................................
Core Watchdog Timer Delay194................................................................................................................................................................
Core Watchdog Service Register (cwsr)195................................................................................................................................................................
Internal Bus Arbitration195................................................................................................................................................................
Arbiter Module Functions196................................................................................................................................................................
Arbitration Algorithms197................................................................................................................................................................
Bus Master Park Register (mpark)198................................................................................................................................................................
Default Bus Master Park Register (mpark)198................................................................................................................................................................
Mpark Field Description199................................................................................................................................................................
System Access Control Unit (sacu)200................................................................................................................................................................
Memory Map/register Definition201................................................................................................................................................................
Sacu Register Memory Map201................................................................................................................................................................
Master Privilege Register (mpr)202................................................................................................................................................................
Mpr[n] Field Descriptions202................................................................................................................................................................
Peripheral Access Control Register (pacrn)203................................................................................................................................................................
Pacr Field Descriptions203................................................................................................................................................................
Pacr Accessctrl Bit Encodings203................................................................................................................................................................
Peripheral Access Control Registers (pacrs)203................................................................................................................................................................
Gpacr Register204................................................................................................................................................................
Gpacr Access_ctrl Bit Encodings205................................................................................................................................................................
Gpacr Address Space206................................................................................................................................................................
Modes Of Operation207................................................................................................................................................................
Normal Pll Mode207................................................................................................................................................................
1:1 Pll Mode208................................................................................................................................................................
External Clock Mode208................................................................................................................................................................
Low-power Mode Operation208................................................................................................................................................................
Clock Module Operation In Low-power Modes208................................................................................................................................................................
Signal Descriptions210................................................................................................................................................................
Extal210................................................................................................................................................................
Pll Block Diagram210................................................................................................................................................................
Signal Properties210................................................................................................................................................................
Xtal211................................................................................................................................................................
Clkout211................................................................................................................................................................
Clkmod[1:0]211................................................................................................................................................................
Rstout211................................................................................................................................................................
Module Memory Map211................................................................................................................................................................
Clock Module Memory Map211................................................................................................................................................................
Synthesizer Control Register (syncr)212................................................................................................................................................................
Syncr Field Descriptions212................................................................................................................................................................
Synthesizer Status Register (synsr)214................................................................................................................................................................
Synsr Field Descriptions215................................................................................................................................................................
System Clock Modes216................................................................................................................................................................
Clock Operation During Reset217................................................................................................................................................................
System Clock Generation217................................................................................................................................................................
Clock Out And Clock In Relationships217................................................................................................................................................................
Pll Operation218................................................................................................................................................................
Crystal Oscillator Example218................................................................................................................................................................
Charge Pump Current And Mfd In Normal Mode Operation219................................................................................................................................................................
Lock Detect Sequence221................................................................................................................................................................
Loss Of Clock Summary222................................................................................................................................................................
Stop Mode Operation223................................................................................................................................................................
Interrupt Controller Modules229................................................................................................................................................................
Coldfire Interrupt Architecture Overview229................................................................................................................................................................
Interrupt Controller Theory Of Operation231................................................................................................................................................................
Interrupt Priority Within A Level231................................................................................................................................................................
Interrupt Controller Base Addresses233................................................................................................................................................................
Interrupt Controller Memory Map233................................................................................................................................................................
Interrupt Pending Registers (iprhn, Iprln)234................................................................................................................................................................
Interrupt Pending Register High (iprhn)235................................................................................................................................................................
Interrupt Pending Register Low (iprln)235................................................................................................................................................................
Iprhn Field Descriptions235................................................................................................................................................................
Iprln Field Descriptions235................................................................................................................................................................
Interrupt Mask Register (imrhn, Imrln)236................................................................................................................................................................
Interrupt Mask Register High (imrhn)236................................................................................................................................................................
Interrupt Mask Register Low (imrln)236................................................................................................................................................................
Imrhn Field Descriptions236................................................................................................................................................................
Interrupt Force Registers (intfrchn, Intfrcln)237................................................................................................................................................................
Interrupt Force Register High (intfrchn)237................................................................................................................................................................
Intfrchn Field Descriptions237................................................................................................................................................................
Imrln Field Descriptions237................................................................................................................................................................
Interrupt Force Register Low (intfrcln)238................................................................................................................................................................
Interrupt Request Level Register (irlrn)238................................................................................................................................................................
Intfrcln Field Descriptions238................................................................................................................................................................
Irqn Field Descriptions238................................................................................................................................................................
Interrupt Acknowledge Level And Priority Register (iacklprn)239................................................................................................................................................................
Iack Level And Priority Register (iacklprn)239................................................................................................................................................................
Iacklprn Field Descriptions239................................................................................................................................................................
Interrupt Control Register (icrnx)240................................................................................................................................................................
Icrnx Field Descriptions240................................................................................................................................................................
Interrupt Source Assignment For Intc0240................................................................................................................................................................
Software And Level N Iack Registers (swiackr, L1iack-l7iack)243................................................................................................................................................................
Interrupt Source Assignment For Intc1243................................................................................................................................................................
Prioritization Between Interrupt Controllers244................................................................................................................................................................
Software And Level N Iack Registers (swiackr, L1iack–l7iack)244................................................................................................................................................................
Swiack And L1iack-l7iack Field Descriptions244................................................................................................................................................................
Low-power Wakeup Operation245................................................................................................................................................................
Introduction247................................................................................................................................................................
Eport Block Diagram247................................................................................................................................................................
Interrupt/general-purpose I/o Pin Descriptions248................................................................................................................................................................
Edge Port Module Operation In Low-power Modes248................................................................................................................................................................
Registers249................................................................................................................................................................
Edge Port Module Memory Map249................................................................................................................................................................
Eport Pin Assignment Register (eppar)250................................................................................................................................................................
Eport Data Direction Register (epddr)250................................................................................................................................................................
Eppar Field Descriptions250................................................................................................................................................................
Eport Port Interrupt Enable Register (epier)251................................................................................................................................................................
Eport Port Data Register (epdr)251................................................................................................................................................................
Epdd Field Descriptions251................................................................................................................................................................
Epier Field Descriptions251................................................................................................................................................................
Eport Port Pin Data Register (eppdr)252................................................................................................................................................................
Eport Port Flag Register (epfr)252................................................................................................................................................................
Epdr Field Descriptions252................................................................................................................................................................
Eppdr Field Descriptions252................................................................................................................................................................
Epfr Field Descriptions253................................................................................................................................................................
Chip Select Module Signals255................................................................................................................................................................
Byte Enables/byte Write Enable Signal Settings256................................................................................................................................................................
Chip Select Operation257................................................................................................................................................................
General Chip Select Operation257................................................................................................................................................................
Connections For External Memory Port Sizes258................................................................................................................................................................
Accesses By Matches In Csars And Dacrs258................................................................................................................................................................
Chip Select Registers259................................................................................................................................................................
D[19:18] External Boot Chip Select Configuration259................................................................................................................................................................
Chip Select Module Registers260................................................................................................................................................................
Chip Select Address Registers (csarn)260................................................................................................................................................................
Chip Select Mask Registers (csmrn)261................................................................................................................................................................
Csarn Field Description261................................................................................................................................................................
Csmrn Field Descriptions261................................................................................................................................................................
Chip Select Control Registers (cscrn)262................................................................................................................................................................
Cscrn Field Descriptions263................................................................................................................................................................
Bus And Control Signals265................................................................................................................................................................
Coldfire Bus Signal Summary265................................................................................................................................................................
Bus Characteristics266................................................................................................................................................................
Data Transfer Operation266................................................................................................................................................................
Signal Relationship To Clkout For Non-dram Access266................................................................................................................................................................
Bus Cycle Execution267................................................................................................................................................................
Chip-select Module Output Timing Diagram267................................................................................................................................................................
Accesses By Matches In Cscrs And Dacrs268................................................................................................................................................................
Data Transfer Cycle States269................................................................................................................................................................
Data Transfer State Transition Diagram269................................................................................................................................................................
Bus Cycle States269................................................................................................................................................................
Read Cycle270................................................................................................................................................................
Read Cycle Flowchart271................................................................................................................................................................
Basic Read Bus Cycle271................................................................................................................................................................
Write Cycle272................................................................................................................................................................
Write Cycle Flowchart272................................................................................................................................................................
Basic Write Bus Cycle272................................................................................................................................................................
Fast Termination Cycles273................................................................................................................................................................
Read Cycle With Fast Termination273................................................................................................................................................................
Write Cycle With Fast Termination273................................................................................................................................................................
Back-to-back Bus Cycles274................................................................................................................................................................
Burst Cycles274................................................................................................................................................................
Line Read Burst (2-1-1-1), External Termination275................................................................................................................................................................
Allowable Line Access Patterns275................................................................................................................................................................
Line Read Burst (2-1-1-1), Internal Termination276................................................................................................................................................................
Line Read Burst (3-2-2-2), External Termination276................................................................................................................................................................
Line Read Burst-inhibited, Fast Termination, External Termination277................................................................................................................................................................
Line Write Burst (2-1-1-1), Internal/external Termination277................................................................................................................................................................
Misaligned Operands278................................................................................................................................................................
Line Write Burst (3-2-2-2) With One Wait State278................................................................................................................................................................
Line Write Burst-inhibited278................................................................................................................................................................
Example Of A Misaligned Longword Transfer (32-bit Port)279................................................................................................................................................................
Example Of A Misaligned Word Transfer (32-bit Port)279................................................................................................................................................................
Mcf5282 Block Diagram With Signal Interfaces282................................................................................................................................................................
Mcf5282 Signal Description283................................................................................................................................................................
Mcf5282 Alphabetical Signal Index288................................................................................................................................................................
Mcf5282 Signals And Pin Numbers Sorted By Function291................................................................................................................................................................
Single-chip Mode297................................................................................................................................................................
External Boot Mode297................................................................................................................................................................
Pin Reset States At Reset (single-chip Mode)297................................................................................................................................................................
Mcf5282 External Signals298................................................................................................................................................................
Transfer Size Encoding300................................................................................................................................................................
Sdram Controller Signals301................................................................................................................................................................
Clock And Reset Signals302................................................................................................................................................................
Chip Configuration Signals302................................................................................................................................................................
External Interrupt Signals303................................................................................................................................................................
Ethernet Module Signals303................................................................................................................................................................
Queued Serial Peripheral Interface (qspi) Signals305................................................................................................................................................................
Flexcan Signals306................................................................................................................................................................
Uart Module Signals306................................................................................................................................................................
General Purpose Timer Signals307................................................................................................................................................................
Dma Timer Signals308................................................................................................................................................................
Analog-to-digital Converter Signals309................................................................................................................................................................
Debug Support Signals310................................................................................................................................................................
Test Signals312................................................................................................................................................................
Processor Status Encoding312................................................................................................................................................................
Power And Reference Signals313................................................................................................................................................................
Definitions315................................................................................................................................................................
Block Diagram And Major Components316................................................................................................................................................................
Synchronous Dram Controller Block Diagram316................................................................................................................................................................
Sdram Controller Operation317................................................................................................................................................................
Sdram Commands317................................................................................................................................................................
Dram Controller Signals318................................................................................................................................................................
Memory Map For Sdramc Registers318................................................................................................................................................................
Synchronous Dram Signal Connections318................................................................................................................................................................
Dram Controller Registers318................................................................................................................................................................
Dram Control Register (dcr)319................................................................................................................................................................
Dcr Field Descriptions319................................................................................................................................................................
Dram Address And Control Register (dacrn)320................................................................................................................................................................
Dacrn Field Descriptions320................................................................................................................................................................
Dram Controller Mask Registers (dmrn)322................................................................................................................................................................
Dmrn Field Descriptions322................................................................................................................................................................
General Synchronous Operation Guidelines323................................................................................................................................................................
Generic Address Multiplexing Scheme323................................................................................................................................................................
Mcf5282 To Sdram Interface (8-bit Port,13-column Address Lines)324................................................................................................................................................................
Mcf5282 To Sdram Interface (16-bit Port, 12-column Address Lines)325................................................................................................................................................................
Mcf5282 To Sdram Interface (32-bit Port, 11-column Address Lines)326................................................................................................................................................................
Mcf5282 To Sdram Interface (32-bit Port, 12-column Address Lines)327................................................................................................................................................................
Sdram Hardware Connections327................................................................................................................................................................
Burst Read Sdram Access328................................................................................................................................................................
Burst Write Sdram Access329................................................................................................................................................................
Auto-refresh Operation330................................................................................................................................................................
Initialization Sequence331................................................................................................................................................................
Self-refresh Operation331................................................................................................................................................................
Sdram Example333................................................................................................................................................................
Sdram Example Specifications333................................................................................................................................................................
Sdram Interface Configuration334................................................................................................................................................................
Dcr Initialization334................................................................................................................................................................
Initialization Values For Dcr334................................................................................................................................................................
Dcr Initialization Values334................................................................................................................................................................
Dacr Initialization335................................................................................................................................................................
Sdram Configuration335................................................................................................................................................................
Dacr Register Configuration335................................................................................................................................................................
Dacr Initialization Values335................................................................................................................................................................
Dmr Initialization336................................................................................................................................................................
Dmr0 Register336................................................................................................................................................................
Dmr0 Initialization Values336................................................................................................................................................................
Mode Register Initialization337................................................................................................................................................................
Mode Register Mapping To Mcf5282 A[31:0]337................................................................................................................................................................
Initialization Code338................................................................................................................................................................
Dma Module Features342................................................................................................................................................................
Dma Signal Diagram342................................................................................................................................................................
Dma Request Control (dmareqc)343................................................................................................................................................................
Dma Request Control Register (dmareqc)343................................................................................................................................................................
Dmareqc Field Description343................................................................................................................................................................
Dma Transfer Overview344................................................................................................................................................................
Dual-address Transfer344................................................................................................................................................................
Dma Controller Module Programming Model345................................................................................................................................................................
Memory Map For Dma Controller Module Registers345................................................................................................................................................................
Source Address Registers (sarn)346................................................................................................................................................................
Destination Address Registers (darn)346................................................................................................................................................................
Byte Count Registers (bcr0–bcr3)347................................................................................................................................................................
Byte Count Registers (bcrn)—bcr24bit = 1347................................................................................................................................................................
Byte Count Registers (bcrn)—bcr24bit = 0347................................................................................................................................................................
Dma Control Registers (dcrn)348................................................................................................................................................................
Dcrn Field Descriptions348................................................................................................................................................................
Dma Status Registers (dsrn)350................................................................................................................................................................
Dsrn Field Descriptions350................................................................................................................................................................
Dma Controller Module Functional Description351................................................................................................................................................................
Transfer Requests (cycle-steal And Continuous Modes)351................................................................................................................................................................
Data Transfer Modes352................................................................................................................................................................
Channel Initialization And Startup353................................................................................................................................................................
Data Transfer354................................................................................................................................................................
Termination355................................................................................................................................................................
Full And Half Duplex Operation358................................................................................................................................................................
Interface Options358................................................................................................................................................................
Address Recognition Options359................................................................................................................................................................
Internal Loopback359................................................................................................................................................................
Fec Top-level Functional Diagram360................................................................................................................................................................
Fec Block Diagram360................................................................................................................................................................
Ecr[ether_en] De-assertion Effect On Fec362................................................................................................................................................................
User Initialization (before Ecr[ether_en])362................................................................................................................................................................
Microcontroller Initialization363................................................................................................................................................................
User Initialization (after Asserting Ecr[ether_en])363................................................................................................................................................................
Fec User Initialization (before Ecr[ether_en])363................................................................................................................................................................
Network Interface Options364................................................................................................................................................................
Mii Mode364................................................................................................................................................................
Wire Mode Configuration364................................................................................................................................................................
Fec Frame Transmission365................................................................................................................................................................
Fec Frame Reception366................................................................................................................................................................
Ethernet Address Recognition367................................................................................................................................................................
Ethernet Address Recognition—receive Block Decisions368................................................................................................................................................................
Hash Algorithm369................................................................................................................................................................
Ethernet Address Recognitionq—microcode Decisions369................................................................................................................................................................
Destination Address To 6-bit Hash370................................................................................................................................................................
Full Duplex Flow Control372................................................................................................................................................................
Pause Frame Field Specification372................................................................................................................................................................
Inter-packet Gap (ipg) Time373................................................................................................................................................................
Collision Handling373................................................................................................................................................................
Internal And External Loopback373................................................................................................................................................................
Ethernet Error-handling Procedure374................................................................................................................................................................
Transmission Errors374................................................................................................................................................................
Transmitter Underrun374................................................................................................................................................................
Retransmission Attempts Limit Expired374................................................................................................................................................................
Reception Errors375................................................................................................................................................................
Top Level Module Memory Map376................................................................................................................................................................
Detailed Memory Map (control/status Registers)376................................................................................................................................................................
Fec Register Memory Map376................................................................................................................................................................
Mib Block Counters Memory Map377................................................................................................................................................................
Mib Counters Memory Map378................................................................................................................................................................
Ethernet Interrupt Event Register (eir)380................................................................................................................................................................
Eir Field Descriptions380................................................................................................................................................................
Interrupt Mask Register (eimr)382................................................................................................................................................................
Eimr Field Descriptions382................................................................................................................................................................
Receive Descriptor Active Register (rdar)383................................................................................................................................................................
Rdar Field Descriptions383................................................................................................................................................................
Transmit Descriptor Active Register (tdar)384................................................................................................................................................................
Ethernet Control Register (ecr)384................................................................................................................................................................
Tdar Field Descriptions384................................................................................................................................................................
Mii Management Frame Register (mmfr)385................................................................................................................................................................
Ecr Field Descriptions385................................................................................................................................................................
Mmfr Field Descriptions386................................................................................................................................................................
Mii Speed Control Register (mscr)387................................................................................................................................................................
Mscr Field Descriptions387................................................................................................................................................................
Mib Control Register (mibc)388................................................................................................................................................................
Programming Examples For Mscr388................................................................................................................................................................
Mibc Field Descriptions388................................................................................................................................................................
Receive Control Register (rcr)389................................................................................................................................................................
Rcr Field Descriptions389................................................................................................................................................................
Transmit Control Register (tcr)390................................................................................................................................................................
Tcr Field Descriptions391................................................................................................................................................................
Physical Address Low Register (palr)392................................................................................................................................................................
Physical Address High Register (paur)392................................................................................................................................................................
Palr Field Descriptions392................................................................................................................................................................
Opcode/pause Duration Register (opd)393................................................................................................................................................................
Paur Field Descriptions393................................................................................................................................................................
Opd Field Descriptions393................................................................................................................................................................
Descriptor Individual Upper Address Register (iaur)394................................................................................................................................................................
Descriptor Individual Lower Address Register (ialr)394................................................................................................................................................................
Iaur Field Descriptions394................................................................................................................................................................
Descriptor Group Upper Address Register (gaur)395................................................................................................................................................................
Ialr Field Descriptions395................................................................................................................................................................
Gaur Field Descriptions395................................................................................................................................................................
Descriptor Group Lower Address Register (galr)396................................................................................................................................................................
Fifo Transmit Fifo Watermark Register (tfwr)396................................................................................................................................................................
Galr Field Descriptions396................................................................................................................................................................
Fifo Receive Bound Register (frbr)397................................................................................................................................................................
Tfwr Field Descriptions397................................................................................................................................................................
Frbr Field Descriptions397................................................................................................................................................................
Fifo Receive Start Register (frsr)398................................................................................................................................................................
Frsr Field Descriptions398................................................................................................................................................................
Receive Descriptor Ring Start (erdsr)398................................................................................................................................................................
Receive Descriptor Ring Start Register (erdsr)399................................................................................................................................................................
Transmit Buffer Descriptor Ring Start Register (etdsr)399................................................................................................................................................................
Erdsr Field Descriptions399................................................................................................................................................................
Receive Buffer Size Register (emrbr)400................................................................................................................................................................
Etdsr Field Descriptions400................................................................................................................................................................
Emrbr Field Descriptions400................................................................................................................................................................
Buffer Descriptors401................................................................................................................................................................
Driver/dma Operation With Buffer Descriptors401................................................................................................................................................................
Ethernet Receive Buffer Descriptor (rxbd)403................................................................................................................................................................
Receive Buffer Descriptor Field Definitions404................................................................................................................................................................
Ethernet Transmit Buffer Descriptor (txbd)405................................................................................................................................................................
Transmit Buffer Descriptor (txbd)406................................................................................................................................................................
Transmit Buffer Descriptor Field Definitions406................................................................................................................................................................
Watchdog Module Operation In Low-power Modes409................................................................................................................................................................
Signals410................................................................................................................................................................
Watchdog Timer Block Diagram410................................................................................................................................................................
Watchdog Control Register (wcr)411................................................................................................................................................................
Watchdog Timer Module Memory Map411................................................................................................................................................................
Watchdog Modulus Register (wmr)412................................................................................................................................................................
Wcr Field Descriptions412................................................................................................................................................................
Watchdog Count Register (wcntr)413................................................................................................................................................................
Wmr Field Descriptions413................................................................................................................................................................
Wcntr Field Descriptions413................................................................................................................................................................
Watchdog Service Register (wsr)414................................................................................................................................................................
Pit Block Diagram415................................................................................................................................................................
Pit Module Operation In Low-power Modes416................................................................................................................................................................
Programmable Interrupt Timer Modules Memory Map417................................................................................................................................................................
Pit Control And Status Register (pcsr)418................................................................................................................................................................
Pcsr Field Descriptions418................................................................................................................................................................
Set-and-forget Timer Operation420................................................................................................................................................................
Pit Modulus Register (pmr)420................................................................................................................................................................
Pit Count Register (pcntr)420................................................................................................................................................................
Free-running Timer Operation421................................................................................................................................................................
Timeout Specifications421................................................................................................................................................................
Counter Reloading From The Modulus Latch421................................................................................................................................................................
Counter In Free-running Mode421................................................................................................................................................................
Interrupt Operation422................................................................................................................................................................
Pit Interrupt Requests422................................................................................................................................................................
Gpt Block Diagram424................................................................................................................................................................
Signal Description425................................................................................................................................................................
Gptn[2:0]425................................................................................................................................................................
Gptn3426................................................................................................................................................................
Syncn426................................................................................................................................................................
Gpt Modules Memory Map426................................................................................................................................................................
Gpt Input Capture/output Compare Select Register (gptios)427................................................................................................................................................................
Gpt Compare Force Register (gpcforc)428................................................................................................................................................................
Gpt Input Compare Force Register (gpcforc)428................................................................................................................................................................
Gptios Field Descriptions428................................................................................................................................................................
Gptcforc Field Descriptions428................................................................................................................................................................
Gpt Output Compare 3 Mask Register (gptoc3m)428................................................................................................................................................................
Gptoc3m Field Descriptions429................................................................................................................................................................
Gptoc3d Field Descriptions429................................................................................................................................................................
Gpt Output Compare 3 Data Register (gptoc3d)429................................................................................................................................................................
Gpt Counter Register (gptcnt)429................................................................................................................................................................
Gptcnt Field Descriptions430................................................................................................................................................................
Gptscr1 Field Descriptions430................................................................................................................................................................
Gpt System Control Register 1 (gptscr)430................................................................................................................................................................
Fast Clear Flag Logic431................................................................................................................................................................
Gpttov Field Description431................................................................................................................................................................
Gpt Toggle-on-overflow Register (gpttov)431................................................................................................................................................................
Gpt Control Register 1 (gptctl)431................................................................................................................................................................
Gptcl1 Field Descriptions432................................................................................................................................................................
Gptlctl2 Field Descriptions432................................................................................................................................................................
Gpt Control Register 2 (gptctl)432................................................................................................................................................................
Gpt Interrupt Enable Register (gptie)432................................................................................................................................................................
Gptie Field Descriptions433................................................................................................................................................................
Gptscr2 Field Descriptions433................................................................................................................................................................
Gpt System Control Register 2 (gptscr)433................................................................................................................................................................
Gptflg1 Field Descriptions434................................................................................................................................................................
Gptflg2 Field Descriptions434................................................................................................................................................................
Gpt Flag Register 1 (gptflg)434................................................................................................................................................................
Gpt Flag Register 2 (gptflg)434................................................................................................................................................................
Gpt Channel Registers (gptcn)435................................................................................................................................................................
Pulse Accumulator Control Register (gptpactl)435................................................................................................................................................................
Gpt Channel[0:3] Register (gptcn)435................................................................................................................................................................
Gptcn Field Descriptions435................................................................................................................................................................
Gptpactl Field Descriptions435................................................................................................................................................................
Pulse Accumulator Flag Register (gptpaflg)436................................................................................................................................................................
Pulse Accumulator Counter Register (gptpacnt)437................................................................................................................................................................
Gptpaflg Field Descriptions437................................................................................................................................................................
Gptpacr Field Descriptions437................................................................................................................................................................
Gpt Port Data Register (gptport)438................................................................................................................................................................
Gpt Port Data Direction Register (gptddr)438................................................................................................................................................................
Gptport Field Descriptions438................................................................................................................................................................
Gptddr Field Descriptions438................................................................................................................................................................
Prescaler439................................................................................................................................................................
Input Capture439................................................................................................................................................................
Output Compare439................................................................................................................................................................
Pulse Accumulator440................................................................................................................................................................
Event Counter Mode440................................................................................................................................................................
Gated Time Accumulation Mode441................................................................................................................................................................
General-purpose I/o Ports441................................................................................................................................................................
Channel 3 Output Compare/pulse Accumulator Logic441................................................................................................................................................................
Gpt Settings And Pin Functions442................................................................................................................................................................
Gpt Interrupt Requests443................................................................................................................................................................
Gpt Channel Interrupts (cnf)444................................................................................................................................................................
Pulse Accumulator Overflow (paovf)444................................................................................................................................................................
Pulse Accumulator Input (paif)444................................................................................................................................................................
Timer Overflow (tof)444................................................................................................................................................................
Key Features448................................................................................................................................................................
Dma Timer Programming Model448................................................................................................................................................................
Dma Timer Block Diagram448................................................................................................................................................................
Capture Mode449................................................................................................................................................................
Reference Compare449................................................................................................................................................................
Output Mode449................................................................................................................................................................
Dma Timer Module Memory Map449................................................................................................................................................................
Dma Timer Mode Registers (dtmrn)450................................................................................................................................................................
Dtmrn Bit Definitions450................................................................................................................................................................
Dma Timer Extended Mode Registers (dtxmrn)451................................................................................................................................................................
Dtxmrn Bit Definitions451................................................................................................................................................................
Dtmrn Field Descriptions451................................................................................................................................................................
Dma Timer Event Registers (dtern)452................................................................................................................................................................
Dtern Bit Definitions452................................................................................................................................................................
Dma Timer Reference Registers (dtrrn)453................................................................................................................................................................
Dma Timer Capture Registers (dtcrn)453................................................................................................................................................................
Dtrrn Bit Definitions453................................................................................................................................................................
Dtern Field Descriptions453................................................................................................................................................................
Dma Timer Counters (dtcnn)454................................................................................................................................................................
Using The Dma Timer Modules454................................................................................................................................................................
Dtcrn Bit Definitions454................................................................................................................................................................
Dtcnn Bit Definitions454................................................................................................................................................................
Code Example455................................................................................................................................................................
Calculating Time-out Values456................................................................................................................................................................
Module Description457................................................................................................................................................................
Interface And Signals458................................................................................................................................................................
Qspi Block Diagram458................................................................................................................................................................
Internal Bus Interface459................................................................................................................................................................
Operation459................................................................................................................................................................
Qspi Input And Output Signals And Functions459................................................................................................................................................................
Qspi Ram460................................................................................................................................................................
Qspi Ram Model461................................................................................................................................................................
Baud Rate Selection462................................................................................................................................................................
Transfer Delays463................................................................................................................................................................
Qspi_clk Frequency As Function Of System Clock And Baud Rate463................................................................................................................................................................
Transfer Length464................................................................................................................................................................
Qspi Registers465................................................................................................................................................................
Qspi Mode Register (qmr)466................................................................................................................................................................
Qmr Field Descriptions466................................................................................................................................................................
Qspi Delay Register (qdlyr)467................................................................................................................................................................
Qspi Clocking And Data Transfer Example467................................................................................................................................................................
Qspi Wrap Register (qwr)468................................................................................................................................................................
Qdlyr Field Descriptions468................................................................................................................................................................
Qwr Field Descriptions468................................................................................................................................................................
Qspi Interrupt Register (qir)469................................................................................................................................................................
Qir Field Descriptions469................................................................................................................................................................
Qspi Data Register (qdr)470................................................................................................................................................................
Qspi Address Register470................................................................................................................................................................
Command Ram Registers (qcr0–qcr15)471................................................................................................................................................................
Qcr0–qcr15 Field Descriptions471................................................................................................................................................................
Programming Example472................................................................................................................................................................
Qspi Timing472................................................................................................................................................................
Simplified Block Diagram475................................................................................................................................................................
Serial Module Overview476................................................................................................................................................................
Uart Module Memory Map477................................................................................................................................................................
Uart Mode Registers 1 (umr1n)478................................................................................................................................................................
Umr1n Field Descriptions479................................................................................................................................................................
Uart Mode Register 2 (umr2n)480................................................................................................................................................................
Umr2n Field Descriptions480................................................................................................................................................................
Uart Status Registers (usrn)481................................................................................................................................................................
Usrn Field Descriptions481................................................................................................................................................................
Uart Clock Select Registers (ucsrn)482................................................................................................................................................................
Uart Command Registers (ucrn)483................................................................................................................................................................
Ucsrn Field Descriptions483................................................................................................................................................................
Ucrn Field Descriptions484................................................................................................................................................................
Uart Receive Buffers (urbn)485................................................................................................................................................................
Uart Transmit Buffers (utbn)485................................................................................................................................................................
Uart Input Port Change Registers (uipcrn)486................................................................................................................................................................
Uart Transmit Buffer (utbn)486................................................................................................................................................................
Uipcrn Field Descriptions486................................................................................................................................................................
Uart Auxiliary Control Register (uacrn)487................................................................................................................................................................
Uart Interrupt Status/mask Registers (uisrn/uimrn)487................................................................................................................................................................
Uacrn Field Descriptions487................................................................................................................................................................
Uart Baud Rate Generator Registers (ubg1n/ubg2n)488................................................................................................................................................................
Uisrn/uimrn Field Descriptions488................................................................................................................................................................
Uart Input Port Register (uipn)489................................................................................................................................................................
Uart Output Port Command Registers (uop1n/uop0n)489................................................................................................................................................................
Uipn Field Descriptions489................................................................................................................................................................
Uop1/uop0 Field Descriptions490................................................................................................................................................................
Uart Module Signal Definitions491................................................................................................................................................................
Uart Block Diagram Showing External And Internal Interface Signals491................................................................................................................................................................
Transmitter/receiver Clock Source492................................................................................................................................................................
Uart/rs-232 Interface492................................................................................................................................................................
Clocking Source Diagram493................................................................................................................................................................
Transmitter And Receiver Operating Modes494................................................................................................................................................................
Transmitter And Receiver Functional Diagram494................................................................................................................................................................
Transmitter Timing Diagram496................................................................................................................................................................
Receiver Timing497................................................................................................................................................................
Looping Modes499................................................................................................................................................................
Automatic Echo499................................................................................................................................................................
Local Loop-back499................................................................................................................................................................
Multidrop Mode500................................................................................................................................................................
Remote Loop-back500................................................................................................................................................................
Multidrop Mode Timing Diagram501................................................................................................................................................................
Bus Operation502................................................................................................................................................................
Programming502................................................................................................................................................................
Uart Interrupts503................................................................................................................................................................
Uart Dma Requests504................................................................................................................................................................
Uart Module Initialization Sequence504................................................................................................................................................................
Uart Mode Programming Flowchart505................................................................................................................................................................
Interface Features511................................................................................................................................................................
Arbitration Procedure514................................................................................................................................................................
Repeated Start514................................................................................................................................................................
Clock Synchronization515................................................................................................................................................................
Handshaking515................................................................................................................................................................
Clock Stretching515................................................................................................................................................................
Synchronized Clock Scl515................................................................................................................................................................
I2adr Field Descriptions516................................................................................................................................................................
I2fdr Field Descriptions517................................................................................................................................................................
I2cr Field Descriptions518................................................................................................................................................................
I2sr Field Descriptions519................................................................................................................................................................
Generation Of Start521................................................................................................................................................................
Post-transfer Software Response521................................................................................................................................................................
Generation Of Stop522................................................................................................................................................................
Generation Of Repeated Start523................................................................................................................................................................
Slave Mode523................................................................................................................................................................
Arbitration Lost524................................................................................................................................................................
Flexcan Block Diagram And Pinout528................................................................................................................................................................
Flexcan Memory Map529................................................................................................................................................................
External Signals529................................................................................................................................................................
The Can System530................................................................................................................................................................
Message Buffers530................................................................................................................................................................
Message Buffer Structure530................................................................................................................................................................
Typical Can System530................................................................................................................................................................
Extended Id Message Buffer Structure531................................................................................................................................................................
Standard Id Message Buffer Structure531................................................................................................................................................................
Common Extended/standard Format Frames532................................................................................................................................................................
Message Buffer Codes For Receive Buffers532................................................................................................................................................................
Message Buffer Codes For Transmit Buffers532................................................................................................................................................................
Message Buffer Memory Map533................................................................................................................................................................
Extended Format Frames533................................................................................................................................................................
Standard Format Frames533................................................................................................................................................................
Functional Overview534................................................................................................................................................................
Transmit Process535................................................................................................................................................................
Receive Process535................................................................................................................................................................
Message Buffer Handling536................................................................................................................................................................
Self-received Frames536................................................................................................................................................................
Remote Frames538................................................................................................................................................................
Overload Frames539................................................................................................................................................................
Time Stamp539................................................................................................................................................................
Listen-only Mode539................................................................................................................................................................
Bit Timing540................................................................................................................................................................
Examples Of System Clock/can Bit-rate/s-clock540................................................................................................................................................................
Flexcan Error Counters541................................................................................................................................................................
Flexcan Initialization Sequence542................................................................................................................................................................
Special Operating Modes543................................................................................................................................................................
Programmer's Model546................................................................................................................................................................
Can Module Configuration Register (canmcr)546................................................................................................................................................................
Canmcr Field Descriptions547................................................................................................................................................................
Flexcan Control Register 0 (canctrl0)548................................................................................................................................................................
Flexcan Control Register 1 (canctrl1)549................................................................................................................................................................
Canctrl0 Field Descriptions549................................................................................................................................................................
Transmit Pin Configuration549................................................................................................................................................................
Prescaler Divide Register (presdiv)550................................................................................................................................................................
Canctrl1 Field Descriptions550................................................................................................................................................................
Flexcan Control Register 2 (canctrl2)551................................................................................................................................................................
Presdiv Field Descriptions551................................................................................................................................................................
Canctrl2 Field Descriptions551................................................................................................................................................................
Free Running Timer (timer)552................................................................................................................................................................
Rx Mask Registers552................................................................................................................................................................
Timer Field Descriptions552................................................................................................................................................................
Mask Examples For Normal/extended Messages552................................................................................................................................................................
Rx Mask Registers (rxgmask, Rx14mask, And Rx15mask)553................................................................................................................................................................
Flexcan Error And Status Register (estat)554................................................................................................................................................................
Rxgmask, Rx14mask, And Rx15mask Field Descriptions554................................................................................................................................................................
Estat Field Descriptions555................................................................................................................................................................
Interrupt Mask Register (imask)556................................................................................................................................................................
Interrupt Flag Register (iflag)557................................................................................................................................................................
Imask Field Descriptions557................................................................................................................................................................
Iflag Field Descriptions557................................................................................................................................................................
Flexcan Receive Error Counter (rxectr)558................................................................................................................................................................
Flexcan Transmit Error Counter (txectr)558................................................................................................................................................................
Rxectr Field Descriptions558................................................................................................................................................................
Txectr Field Descriptions558................................................................................................................................................................
Mcf5282 Ports Module Block Diagram560................................................................................................................................................................
External Signal Description562................................................................................................................................................................
Mcf5282 Ports External Signals562................................................................................................................................................................
Register Overview564................................................................................................................................................................
Mcf5282 Ports Module Memory Map564................................................................................................................................................................
Port Output Data Registers (6-bit)566................................................................................................................................................................
Port Output Data Registers (4-bit)567................................................................................................................................................................
Port Data Direction Registers (8-bit)567................................................................................................................................................................
Portn (8-bit, 7-bit, 6-bit, And 4-bit) Field Descriptions567................................................................................................................................................................
Port Data Direction Register (7-bit)568................................................................................................................................................................
Port Data Direction Registers (4-bit)568................................................................................................................................................................
Ddrn (8-bit, 6-bit, And 4-bit) Field Descriptions568................................................................................................................................................................
Port Pin Data/set Data Registers (6-bit)569................................................................................................................................................................
Port Pin Data/set Data Registers (4-bit)570................................................................................................................................................................
Port Clear Output Data Registers (8-bit)570................................................................................................................................................................
Portnp/setn (8-bit, 6-bit, And 4-bit) Field Descriptions570................................................................................................................................................................
Port Clear Output Data Register (7-bit)571................................................................................................................................................................
Port Clear Output Data Registers (4-bit)571................................................................................................................................................................
Clrn (8-bit,7-bit, 6-bit, And 4-bit) Field Descriptions571................................................................................................................................................................
Port B/c/d Pin Assignment Register (pbcdpar)572................................................................................................................................................................
Pbcdpar Field Descriptions572................................................................................................................................................................
Reset Values For Pbcdpar Bits572................................................................................................................................................................
Port E Pin Assignment Register (pepar)573................................................................................................................................................................
Pepar Field Descriptions573................................................................................................................................................................
Reset Values For Pepar Bits And Fields574................................................................................................................................................................
Port F Pin Assignment Register (pfpar)575................................................................................................................................................................
Pfpar Field Descriptions575................................................................................................................................................................
Port J Pin Assignment Register (pjpar)576................................................................................................................................................................
Pjpar Field Descriptions576................................................................................................................................................................
Port Sd Pin Assignment Register (psdpar)577................................................................................................................................................................
Port As Pin Assignment Register (paspar)577................................................................................................................................................................
Psdpar Field Descriptions577................................................................................................................................................................
Port Eh/el Pin Assignment Register (pehlpar)578................................................................................................................................................................
Paspar Field Descriptions578................................................................................................................................................................
Port Qs Pin Assignment Register (pqspar)579................................................................................................................................................................
Pehlpar Field Descriptions579................................................................................................................................................................
Pqspar Field Description579................................................................................................................................................................
Port Tc Pin Assignment Register (ptcpar)580................................................................................................................................................................
Ptcpar Field Descriptions580................................................................................................................................................................
Port Td Pin Assignment Register (ptdpar)581................................................................................................................................................................
Ptdpar Field Descriptions581................................................................................................................................................................
Port Ua Pin Assignment Register (puapar)582................................................................................................................................................................
Puapar Field Descriptions582................................................................................................................................................................
Port Digital I/o Timing583................................................................................................................................................................
Digital Input Timing583................................................................................................................................................................
Initialization/application Information584................................................................................................................................................................
Digital Output Timing584................................................................................................................................................................
Qadc Block Diagram586................................................................................................................................................................
Debug Mode587................................................................................................................................................................
Port Qa Signal Functions588................................................................................................................................................................
Port Qb Signal Functions589................................................................................................................................................................
Qadc Input And Output Signals589................................................................................................................................................................
External Trigger Input Signals590................................................................................................................................................................
Multiplexed Address Output Signals590................................................................................................................................................................
Multiplexed Analog Input Signals590................................................................................................................................................................
Voltage Reference Signals591................................................................................................................................................................
Dedicated Analog Supply Signals591................................................................................................................................................................
Dedicated Digital I/o Port Supply Signal591................................................................................................................................................................
Multiplexed Analog Input Channels591................................................................................................................................................................
Qadc Module Configuration Register (qadcmcr)592................................................................................................................................................................
Qadc Memory Map592................................................................................................................................................................
Qadc Test Register (qadctest)593................................................................................................................................................................
Port Data Registers (portqa And Portqb)593................................................................................................................................................................
Qadcmcr Field Descriptions593................................................................................................................................................................
Port Qa And Qb Data Direction Register (ddrqa And Ddrqb)594................................................................................................................................................................
Qadc Port Qa Data Register (portqa)594................................................................................................................................................................
Qadc Port Qb Data Register (portqb)594................................................................................................................................................................
Control Registers595................................................................................................................................................................
Qadc Port Qa Data Direction Register (ddrqa)595................................................................................................................................................................
Port Qb Data Direction Register (ddrqb)595................................................................................................................................................................
Qadc Control Register 0 (qacr0)596................................................................................................................................................................
Qacr0 Field Descriptions596................................................................................................................................................................
Qadc Control Register 1 (qacr1)598................................................................................................................................................................
Qacr1 Field Descriptions598................................................................................................................................................................
Queue 1 Operating Modes599................................................................................................................................................................
Qadc Control Register 2 (qacr2)601................................................................................................................................................................
Qacr2 Field Descriptions602................................................................................................................................................................
Queue 2 Operating Modes602................................................................................................................................................................
Status Registers603................................................................................................................................................................
Qadc Status Register 0 (qasr0)606................................................................................................................................................................
Qasr0 Field Descriptions607................................................................................................................................................................
Ccw Pause Bit Response608................................................................................................................................................................
Queue Status608................................................................................................................................................................
Queue Status Transition609................................................................................................................................................................
Conversion Command Word Table (ccw)610................................................................................................................................................................
Qadc Status Register 1 (qasr1)610................................................................................................................................................................
Qasr1 Field Descriptions610................................................................................................................................................................
Ccw Field Descriptions611................................................................................................................................................................
Input Sample Times612................................................................................................................................................................
Non-multiplexed Channel Assignments And Signal Designations612................................................................................................................................................................
Result Registers613................................................................................................................................................................
Right-justified Unsigned Result Register (rjurr)613................................................................................................................................................................
Multiplexed Channel Assignments And Signal Designations613................................................................................................................................................................
Left-justified Signed Result Register (ljsrr)614................................................................................................................................................................
Rjurr Field Descriptions614................................................................................................................................................................
Ljsrr Field Descriptions614................................................................................................................................................................
Result Coherency615................................................................................................................................................................
External Multiplexing615................................................................................................................................................................
Left-justified Unsigned Result Register (ljurr)615................................................................................................................................................................
Ljurr Field Descriptions615................................................................................................................................................................
External Multiplexing Configuration617................................................................................................................................................................
Analog Subsystem618................................................................................................................................................................
Analog Input Channels618................................................................................................................................................................
Qadc Analog Subsystem Block Diagram619................................................................................................................................................................
Conversion Timing620................................................................................................................................................................
Bypass Mode Conversion Timing620................................................................................................................................................................
Digital Control Subsystem621................................................................................................................................................................
Queue Priority Timing Examples622................................................................................................................................................................
Qadc Queue Operation With Pause623................................................................................................................................................................
Trigger Events624................................................................................................................................................................
Status Bits624................................................................................................................................................................
Ccw Priority Situation 1625................................................................................................................................................................
Ccw Priority Situation 2626................................................................................................................................................................
Ccw Priority Situation 3626................................................................................................................................................................
Ccw Priority Situation 4627................................................................................................................................................................
Ccw Priority Situation 5627................................................................................................................................................................
Ccw Priority Situation 6628................................................................................................................................................................
Ccw Priority Situation 7628................................................................................................................................................................
Ccw Priority Situation 8629................................................................................................................................................................
Ccw Priority Situation 9629................................................................................................................................................................
Ccw Priority Situation 10630................................................................................................................................................................
Ccw Priority Situation 11630................................................................................................................................................................
Ccw Freeze Situation 12631................................................................................................................................................................
Ccw Freeze Situation 13631................................................................................................................................................................
Ccw Freeze Situation 14631................................................................................................................................................................
Ccw Freeze Situation 15631................................................................................................................................................................
Ccw Freeze Situation 16632................................................................................................................................................................
Ccw Freeze Situation 17632................................................................................................................................................................
Ccw Freeze Situation 18632................................................................................................................................................................
Ccw Freeze Situation 19632................................................................................................................................................................
Boundary Conditions633................................................................................................................................................................
Scan Modes634................................................................................................................................................................
Disabled Mode634................................................................................................................................................................
Reserved Mode634................................................................................................................................................................
Single-scan Modes634................................................................................................................................................................
Continuous-scan Modes638................................................................................................................................................................
Qadc Clock (qclk) Generation641................................................................................................................................................................
Periodic/interval Timer642................................................................................................................................................................
Qadc Clock Subsystem Functions642................................................................................................................................................................
Conversion Command Word Table643................................................................................................................................................................
Qadc Conversion Queue Operation644................................................................................................................................................................
Result Word Table646................................................................................................................................................................
Signal Connection Considerations646................................................................................................................................................................
Analog Reference Signals647................................................................................................................................................................
Analog Power Signals647................................................................................................................................................................
Equivalent Analog Input Circuitry647................................................................................................................................................................
Conversion Timing Schemes648................................................................................................................................................................
Errors Resulting From Clipping648................................................................................................................................................................
External Positive Edge Trigger Mode Timing With Pause649................................................................................................................................................................
Gated Mode, Single Scan Timing650................................................................................................................................................................
Analog Supply Filtering And Grounding651................................................................................................................................................................
Gated Mode, Continuous Scan Timing651................................................................................................................................................................
Star-ground At The Point Of Power Supply Origin652................................................................................................................................................................
Accommodating Positive/negative Stress Conditions653................................................................................................................................................................
Input Signal Subjected To Negative Stress653................................................................................................................................................................
Input Signal Subjected To Positive Stress654................................................................................................................................................................
Analog Input Considerations655................................................................................................................................................................
External Multiplexing Of Analog Signal Sources656................................................................................................................................................................
Analog Input Pins657................................................................................................................................................................
Electrical Model Of An A/d Input Signal657................................................................................................................................................................
External Circuit Settling Time To 1/2 Lsb658................................................................................................................................................................
Interrupt Sources660................................................................................................................................................................
Qadc Status Flags And Interrupt Sources660................................................................................................................................................................
Rsti662................................................................................................................................................................
Rsto662................................................................................................................................................................
Reset Controller Block Diagram662................................................................................................................................................................
Reset Controller Signal Properties662................................................................................................................................................................
Reset Control Register (rcr)663................................................................................................................................................................
Reset Controller Memory Map663................................................................................................................................................................
Reset Status Register (rsr)664................................................................................................................................................................
Rsr Field Descriptions665................................................................................................................................................................
Reset Sources666................................................................................................................................................................
Reset Source Summary666................................................................................................................................................................
Watchdog Timer Reset667................................................................................................................................................................
Software Reset667................................................................................................................................................................
Reset Control Flow668................................................................................................................................................................
Concurrent Resets670................................................................................................................................................................
Processor/debug Module Interface673................................................................................................................................................................
Clkout Timing674................................................................................................................................................................
Debug Module Signals674................................................................................................................................................................
Real-time Trace Support675................................................................................................................................................................
Begin Execution Of Taken Branch (pst = 0x5)676................................................................................................................................................................
Example Jmp Instruction Output On Pst/ddata677................................................................................................................................................................
Debug Programming Model678................................................................................................................................................................
Revision A Shared Debug Resources679................................................................................................................................................................
Bdm/breakpoint Registers679................................................................................................................................................................
Rev. A Shared Bdm/breakpoint Hardware679................................................................................................................................................................
Address Attribute Trigger Register (aatr)680................................................................................................................................................................
Aatr Field Descriptions680................................................................................................................................................................
Address Breakpoint Registers (ablr, Abhr)681................................................................................................................................................................
Configuration/status Register (csr)682................................................................................................................................................................
Ablr Field Description682................................................................................................................................................................
Abhr Field Description682................................................................................................................................................................
Csr Field Descriptions683................................................................................................................................................................
Data Breakpoint/mask Registers (dbr/dbmr)684................................................................................................................................................................
Program Counter Breakpoint/mask Registers (pbr, Pbmr)685................................................................................................................................................................
Dbr Field Descriptions685................................................................................................................................................................
Dbmr Field Descriptions685................................................................................................................................................................
Access Size And Operand Data Location685................................................................................................................................................................
Trigger Definition Register (tdr)686................................................................................................................................................................
Program Counter Breakpoint Register (pbr)686................................................................................................................................................................
Program Counter Breakpoint Mask Register (pbmr)686................................................................................................................................................................
Pbr Field Descriptions686................................................................................................................................................................
Pbmr Field Descriptions686................................................................................................................................................................
Tdr Field Descriptions687................................................................................................................................................................
Background Debug Mode (bdm)688................................................................................................................................................................
Cpu Halt688................................................................................................................................................................
Bdm Serial Interface690................................................................................................................................................................
Bdm Serial Interface Timing690................................................................................................................................................................
Receive Bdm Packet691................................................................................................................................................................
Transmit Bdm Packet691................................................................................................................................................................
Receive Bdm Packet Field Description691................................................................................................................................................................
Transmit Bdm Packet Field Description691................................................................................................................................................................
Bdm Command Set692................................................................................................................................................................
Bdm Command Summary692................................................................................................................................................................
Bdm Command Format693................................................................................................................................................................
Bdm Field Descriptions693................................................................................................................................................................
Command Sequence Diagram694................................................................................................................................................................
Nop Command Format703................................................................................................................................................................
Control Register Map704................................................................................................................................................................
Definition Of Drc Encoding—read708................................................................................................................................................................
Real-time Debug Support709................................................................................................................................................................
Theory Of Operation709................................................................................................................................................................
Ddata[3:0]/csr[bstat] Breakpoint Response709................................................................................................................................................................
Concurrent Bdm And Processor Operation711................................................................................................................................................................
Processor Status, Ddata Definition712................................................................................................................................................................
User Instruction Set712................................................................................................................................................................
Pst/ddata Specification For User-mode Instructions712................................................................................................................................................................
Pst/ddata Specification For Mac Instructions715................................................................................................................................................................
Supervisor Instruction Set716................................................................................................................................................................
Pst/ddata Specification For Supervisor-mode Instructions716................................................................................................................................................................
Recommended Bdm Connector717................................................................................................................................................................
Motorola-recommended Bdm Pinout718................................................................................................................................................................
Chip Configuration Module Block Diagram720................................................................................................................................................................
Rcon721................................................................................................................................................................
D[26:24, 21, 19:16] (reset Configuration Override)721................................................................................................................................................................
Write-once Bits Read/write Accessibility722................................................................................................................................................................
Chip Configuration Module Memory Map722................................................................................................................................................................
Chip Configuration Register (ccr)723................................................................................................................................................................
Reset Configuration Register (rcon)724................................................................................................................................................................
Rcon Field Descriptions724................................................................................................................................................................
Rcsc Chip Select Configuration725................................................................................................................................................................
Bootps Port Size Configuration725................................................................................................................................................................
Reset Configuration726................................................................................................................................................................
Chip Identification Register (cir)726................................................................................................................................................................
Cir Field Description726................................................................................................................................................................
Reset Configuration Pin States During Reset727................................................................................................................................................................
Configuration During Reset727................................................................................................................................................................
Chip Mode Selection728................................................................................................................................................................
Boot Device Selection729................................................................................................................................................................
Output Pad Strength Configuration729................................................................................................................................................................
Clock Mode Selection729................................................................................................................................................................
Chip Configuration Mode Selection729................................................................................................................................................................
Output Pad Driver Strength Selection729................................................................................................................................................................
Chip Select Configuration730................................................................................................................................................................
Jtag Block Diagram732................................................................................................................................................................
Detailed Signal Description733................................................................................................................................................................
Pin Function Selected733................................................................................................................................................................
Signal State To The Disable Module734................................................................................................................................................................
Idcode Register735................................................................................................................................................................
Idcode Register Field Descriptions736................................................................................................................................................................
Jtag Module737................................................................................................................................................................
Tap Controller737................................................................................................................................................................
Jtag Instructions738................................................................................................................................................................
Tap Controller State Machine Flow738................................................................................................................................................................
Restrictions741................................................................................................................................................................
Nonscan Chain Operation742................................................................................................................................................................
Mechanical Data743................................................................................................................................................................
Pinout744................................................................................................................................................................
Mcf5282 Pinout (256 Mapbga)744................................................................................................................................................................
Mcf5282 Signal Description By Pin Number745................................................................................................................................................................
Ordering Information749................................................................................................................................................................
Mapbga Package Dimensions749................................................................................................................................................................
Orderable Part Numbers749................................................................................................................................................................
Maximum Ratings751................................................................................................................................................................
Absolute Maximum Ratings,751................................................................................................................................................................
Thermal Characteristics753................................................................................................................................................................
Dc Electrical Specifications754................................................................................................................................................................
Phase Lock Loop Electrical Specifications756................................................................................................................................................................
Pll Electrical Specifications756................................................................................................................................................................
Qadc Electrical Characteristics757................................................................................................................................................................
Qadc Absolute Maximum Ratings757................................................................................................................................................................
Qadc Electrical Specifications (operating)757................................................................................................................................................................
Flash Memory Characteristics759................................................................................................................................................................
Qadc Conversion Specifications (operating)759................................................................................................................................................................
Sgfm Flash Program And Erase Characteristics759................................................................................................................................................................
External Interface Timing Characteristics760................................................................................................................................................................
Sgfm Flash Module Life Characteristics760................................................................................................................................................................
Processor Bus Input Timing Specifications760................................................................................................................................................................
Processor Bus Output Timing Specifications761................................................................................................................................................................
General Input Timing Requirements761................................................................................................................................................................
External Bus Output Timing Specifications761................................................................................................................................................................
Read/write (internally Terminated) Timing763................................................................................................................................................................
Read Bus Cycle Terminated By Ta764................................................................................................................................................................
Read Bus Cycle Terminated By Tea765................................................................................................................................................................
Sdram Read Cycle766................................................................................................................................................................
Sdram Timing766................................................................................................................................................................
General Purpose I/o Timing767................................................................................................................................................................
Sdram Write Cycle767................................................................................................................................................................
Gpio Timing ,767................................................................................................................................................................
Reset And Configuration Override Timing768................................................................................................................................................................
Gpio Timing768................................................................................................................................................................
Rsti And Configuration Override Timing769................................................................................................................................................................
Fast Ethernet Ac Timing Specifications770................................................................................................................................................................
Mii Transmit Signal Timing (etxd[3:0], Etxen, Etxer, Etxclk)771................................................................................................................................................................
Mii Receive Signal Timing Diagram771................................................................................................................................................................
Mii Receive Signal Timing771................................................................................................................................................................
Mii Transmit Signal Timing Diagram772................................................................................................................................................................
Mii Async Inputs Timing Diagram772................................................................................................................................................................
Mii Async Inputs Signal Timing772................................................................................................................................................................
Mii Serial Management Channel Timing Diagram773................................................................................................................................................................
Mii Serial Management Channel Timing773................................................................................................................................................................
Dma Timer Module Ac Timing Specifications774................................................................................................................................................................
Qspi Electrical Specifications774................................................................................................................................................................
Qspi Modules Ac Timing Specifications774................................................................................................................................................................
Jtag And Boundary Scan Timing775................................................................................................................................................................
Test Clock Input Timing775................................................................................................................................................................
Boundary Scan (jtag) Timing776................................................................................................................................................................
Test Access Port Timing776................................................................................................................................................................
Trst Timing776................................................................................................................................................................
Debug Ac Timing Specifications777................................................................................................................................................................
Bkpt Timing777................................................................................................................................................................
Real-time Trace Ac Timing778................................................................................................................................................................
Bdm Serial Port Ac Timing778................................................................................................................................................................

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