Motorola MPC860 PowerQUICC User Manual page 723

Table 26-8. Asynchronous HDLC SCCS Field Descriptions
Bits Name
0Ð6 Ñ Reserved, should be cleared.
7 ID Idle status. Set when RXD has been a logic one for at least a full character time.
0 The line is not idle.
1 The line is idle.
26.13.3 Asynchronous HDLC Mode Register (PSMR)
When the SCC is in asynchronous HDLC mode, the PSMR, shown in Figure 26-6, acts as
the asynchronous HDLC mode register.
Bit 0 1 2
Field FLC Ñ
Reset
R/w
Addr
Figure 26-6. Asynchronous HDLC Mode Register (PSMR)
Table 26-9 describes PSMR Þelds.
Bits Name
0 FLC Flow control
0 Normal operation.
1 Asynchronous ßow control. When CTS is negated, the transmitter stops at the end of the current
character. If CTS remains negated past the middle of the character, the next full character is sent
before transmission stops. If CTS is reasserted, transmission resumes from where it stopped and no
CTS lost error is reported. Only idle characters are sent while CTS is negated.
1 Ñ Reserved, should be cleared.
2Ð3 CHLN Character length. On other protocols CHLN is the number of data bits in a character. For asynchronous
HDLC mode and IrDA modes, CHLN must be set to 0b11 (indicating a character length of 8 bits).
4Ð15 Ñ Reserved, should be cleared.
26.14 SCC Asynchronous HDLC RxBDs
The CPM uses the RxBD, shown in Figure 26-7, to report on received data. An example of
the RxBD process is shown in Figure 26-2.
MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA
3 4 5 6
CHLN
0xA08 (PSMR1), 0xA28 (PSMR2), 0xA48 (PSMR3), 0xA68 (PSMR4)
Table 26-9. PSMR Field Descriptions
Part V. The Communications Processor Module
Description
7 8 9 10 11
Ñ
0
R/W
Description
12 13 14 15
26-11