Motorola MPC860 PowerQUICC User Manual page 115

PowerPC Microprocessor Module
Intended Audience
Part II is intended for users who need to understand the programming model of the
embedded microprocessor. It assumes some familiarity with RISC architectures.
Contents
Part II describes the PowerPC microprocessor embedded in the MPC860. It provides
detailed information on the registers and instructions that are implemented, the memory
management unit (MMU), cache model, exception model, and an overview of instruction
timing.
It contains the following chapters:
¥ Chapter 4, ÒThe PowerPC Core,Ó provides an overview of the MPC860 core,
summarizing topics described in further detail in subsequent chapters in Part II.
¥ Chapter 5, ÒPowerPC Core Register Set,Ó describes the hardware registers
accessible to the MPC860 core. These include both architecturally-deÞned and
MPC860-speciÞc registers.
¥ Chapter 6, ÒMPC860 Instruction Set,Ó describes the PowerPC instructions
implemented on the MPC860, including MPC860-speciÞc features.
¥ Chapter 7, ÒExceptions,Ó describes the PowerPC exception model as it is
implemented on the MPC860.
¥ Chapter 8, ÒInstruction and Data Caches,Ó describes the organization of the on-chip
instruction and data caches, cache control, various cache operations, and the
interaction between the caches, the load/store unit (LSU), the instruction sequencer,
and the system interface unit (SIU).
¥ Chapter 9, ÒMemory Management Unit (MMU)Ó describes how the PowerPC
MMU model is implemented on the MPC860. Although the MPC860 MMU is based
on the PowerPC MMU model, it differs greatly in many respects, which are
described in this chapter.
MOTOROLA Part II. PowerPC Microprocessor Module
Part II
II-i