Motorola MPC860 PowerQUICC User Manual page 290

Part III. Configuration
Functionality
Exception Vector 0x100
Core input NMI
SIMASK Not used, except for enabling SIVEC
SIVEC Not normally used. If used, SIMASK[IRQ0] must
be set.
SWT interrupts behave similarly, in that they jump to the system reset vector (0x100).
However, they are not affected by any interrupt controller registers.
Although NMI causes a jump to the system reset vector, no other reset action is taken. For
information on recoverability of NMI, refer to the explanation of MSR[RI].
11.5.4 Programming the SIU Interrupt Controller
The SIUÕs interrupt controller includes the SIU interrupt pending register (SIPEND), SIU
interrupt mask register (SIMASK), SIU interrupt edge/level register (SIEL), and SIU
interrupt vector register (SIVEC) registers. These are described in the following sections.
11.5.4.1 SIU Interrupt Pending Register (SIPEND)
SIU interrupt pending register (SIPEND) bits, shown in Figure 11-10, correspond to
interrupt requests.
The LVL[0Ð7] bits are associated with internal exceptions, and when set indicate that an
interrupt service is requested if they are not masked by the corresponding SIMASK bit.
These bits reßect the status of the internal requesting device and are cleared when the
appropriate actions are software-initiated in the device. Writing to these bits has no effect.
Note that IRQ0 can be masked in only a very limited sense. If SIEL[ED0] = 1,
edge-sensitive, and SIPEND[IRQ0] is not cleared in the ISR, further assertions of IRQ0 are
masked.
The IRQ[0Ð7] bits are associated with the IRQ signals, and their function depends on the
sensitivity deÞned for them in SIEL.
¥ When an IRQ pin is deÞned as a level interrupt, the corresponding IRQ bit behaves
like an LVL bit.
¥ If an IRQ pin is deÞned as an edge interrupt, the corresponding bit being set
indicates that a falling edge was detected on the line. These bits are reset by writing
ones to them.
11-16
Table 11-8. IRQ0 Versus IRQx Operation
IRQ0
MPC860 PowerQUICC UserÕs Manual
IRQx
0x500
External interrupt
Used for masking
Supplies the interrupt code so the core knows
the interrupt source.
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