Motorola MPC860 PowerQUICC User Manual page 187

Table 7-13. Register Settings after an Instruction TLB Miss Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 0Ð3 0
4 1
10 1
11Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Others 0
Some instruction TLB registers are set to the values described in Chapter 9, ÒMemory
Management Unit (MMU).Ó Execution resumes at offset 0x01100 from the base address
indicated by MSR[IP].
7.1.3.3 Data TLB Miss Exception (0x01200)
This type of exception occurs when MSR[DR] = 1 and an attempt is made to access a page
whose effective page number cannot be translated by TLB. The following registers are set:
Table 7-14. Register Settings after a Data TLB Miss Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1Ð4 0
10Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Others 0
Some instruction TLB registers are set to the values described in Chapter 9, ÒMemory
Management Unit (MMU).Ó Execution resumes at offset 0x01200 from the base address
indicated by MSR[IP].
7.1.3.4 Instruction TLB Error Exception (0x01300)
This type of exception occurs as a result of one of the following conditions if MSR[IR] = 1:
¥ The EA cannot be translated. Either the segment or page valid bit of this page is
cleared in the translation table. Note that although the MPC860 does not implement
segment registers as they are deÞned by the OEA, the concept of segment is retained
as the memory space accessible to the level-one table descriptors.
¥ The fetch access violates memory protection.
¥ The fetch access is to guarded memory.
MOTOROLA
Part II. PowerPC Microprocessor Module
Setting
Setting
Chapter 7. Exceptions 7-13