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Part V. The Communications Processor Module
Table 22-1. GSMR_H Field Descriptions (Continued)
Bit
Name
28Ð29 SYNL Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR)
deÞnition in the BISYNC (Section 27.9, ÒSending and Receiving the Synchronization SequenceÓ) and
totally transparent (Section 29.4.2.1, ÒIn-line Synchronization PatternÓ) chapters.
00 An external sync (CD) is used instead of the sync pattern in the DSR.
01 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR. This sync and
additional syncs can be stripped by programming the SCCÕs parameter RAM for character
recognition.
10 8-bit sync. Should be chosen along with the BISYNC protocol to implement mono-sync. The
receiver synchronizes on an 8-bit sync pattern in the DSR.
11 16-bit sync. Also called BISYNC. The receiver synchronizes on a 16-bit sync pattern stored in the
DSR.
30
RTSM RTS mode. Determines whether ßags or idles are to be sent. Can be changed on-the-ßy.
0 Send idles between frames as deÞned by the protocol and the TEND bit. RTS is negated between
frames (default).
1 Send ßags/syncs between frames according to the protocol. RTS is always asserted whenever the
SCC is enabled.
31
RSYN Receive synchronization timing (totally transparent mode only).
0 Normal operation.
1 If CDS = 1
Figure 22-3 shows GSMR_L.
Bit
0
1
2
Field
SIR
EDGE
Reset
R/W
Addr
0xA00 (GSMR_L1), 0xA20 (GSMR_L2), 0xA40 (GSMR_L3), 0xA60 (GSMR_L4)
Bit
16
17
18
Field
RDCR
Reset
R/W
Addr
0xA02 (GSMR_L1), 0xA22 (GSMR_L2), 0xA42 (GSMR_L3), 0xA62 (GSMR_L4)
Figure 22-3. GSMR_LÑGeneral SCC Mode Register (Low Order)
22-6
,
CD should be asserted on the second bit of the Rx frame rather than on the Þrst.
3
4
5
6
TCI
TSNC
RINV TINV
19
20
21
22
RENC
TENC
MPC860 PowerQUICC UserÕs Manual
Description
7
8
9
10
TPL
0
R/W
23
24
25
26
DIAG
ENR ENT
0
R/W
11
12
13
14
TPP
TEND
TDCR
27
28
29
30
MODE
MOTOROLA
15
31
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