Motorola MPC860 PowerQUICC User Manual page 757

Part V. The Communications Processor Module
signal to signify that the current frame should be discarded. Internal address recognition
logic and an external CAM can be used simultaneously; see Section 28.11, ÒSCC Ethernet
Address Recognition.Ó
Note that the IDMA and the Ethernet CAM interfaces both use the SDACK(1Ð2) signals.
If both functions are needed, the function code registers (FCRs) of the IDMA and the
Ethernet SCC can be programmed with unique values for the address type, AT[1Ð3].
External logic can then distinguish between the two interfaces.
28.7.1 Serial CAM Interface (SCC1 and SCC2 Only)
When the start frame delimiter is recognized, the MPC860 asserts RSTRT for one bit time
on the second destination address bit. The CAM control logic uses RSTRT (in combination
with RXD and RCLK) to store the destination or source address and to generate writes to
the CAM for address recognition. In addition, RENA supplied from the EEST can abort the
comparison if a collision occurs on the receive frame.
After the comparison, if CAM control logic asserts REJECT for the current receive frame,
the Ethernet controller immediately stops writing data to system memory and reuses the
buffer(s) for the next frame. If the CAM accepts the frame, CAM control logic does nothing
and REJECT is not asserted. REJECT must be asserted before the end of the receive frame.
The CAM control logic can provide additional information on PB(16Ð23). The Ethernet
controller writes this additional byte to memory during the last SDMA write if PSMR[SIP]
is set. The Ethernet controller samples this information tag as the last FCS byte is read from
the receive FIFO. The CAM control logic must provide the information tag no later than
when RENA is negated at the end of a noncollision frame and should be held stable on
PB(16Ð23) until SDACK(1Ð2) indicate that the tag byte is being written to memory.
MOTOROLA Chapter 28. SCC Ethernet Mode 28-9