Motorola MPC860 PowerQUICC User Manual page 618

Part V. The Communications Processor Module
L1CLK
L1SYNC
L1RXD
L1TXD
L1CLK
L1SYNC
L1RXD
L1TXD
Notes:
1. Clocks are not to scale.
2. LIRQx and L1GRx are not shown.
Note that previous versions of Motorola IDL-deÞned bit functions called auxiliary (A) and
maintenance (M) were removed from the IDL deÞnition when it was concluded that the
IDL control channel would be out-of-band. These functions were deÞned as a subset of the
Motorola SPI format called serial control port (SCP). To implement the A and M bits as
originally deÞned, program the TSA to access these bits and route them transparently to an
SCC or SMC. Use the SPI to perform out-of-band signaling.
The MPC860 supports all channels of the IDL bus in the basic rate. Each bit in the IDL
frame can be routed to any SCC and SMC or they can assert a strobe output that supports
an external device.
The MPC860 supports the request-grant method for contention detection on the D channel
of the IDL basic rate and when the MPC860 has data to send on the D channel, it asserts
L1RQx. The physical layer device monitors the physical layer bus for activity on the D
channel and indicates that the channel is free by asserting L1GRx. The MPC860 samples
L1GRx when the IDL sync signal (L1RSYNCx) is asserted. If L1GRx is asserted, the
MPC860 sends the Þrst zero of the opening ßag in the Þrst bit of the D channel. If a collision
is detected on the D channel, the physical layer device negates L1GRx. The MPC860 then
stops its transmission and resends the frame when L1GRx is reasserted. This procedure is
handled automatically for the Þrst two buffers of a frame.
21-30
10-Bit IDL
B1 D1
B1 D1
8-Bit IDL
B1
B1
Figure 21-26. IDL Bus Signals
MPC860 PowerQUICC UserÕs Manual
B2
B2
B2 D1 D2
B2 D1 D2
D2
D2
MOTOROLA