Motorola MPC860 PowerQUICC User Manual page 538

Part V. The Communications Processor Module
Interrupt Controller
4 Timers
Parallel I/O Ports
4 Baud Rate Generators
SCC1
The following lists the CPMÕs main features:
¥ Communications processor (CP)
Ñ Dual-port RAM
Ñ Internal ROM
Ñ DSP functions with 16-bit multiply/accumulate hardware (MAC)
Ñ DMA control for all communications channels
Ñ Two independent DMA channels for memory-to-memory transfers or interfacing
external peripherals
Ñ RISC timer tables
¥ Four full-duplex serial communications controllers (SCCs) that support the
following:
Ñ UART protocol (asynchronous or synchronous)
Ñ HDLC protocol
Ñ AppleTalk protocol
Ñ Asynchronous HDLC protocol
Ñ BISYNC protocol
18-2
Peripheral Bus
SCC2 SCC3 SCC4
Serial Interface and Time-Slot Assigner
Figure 18-1. CPM Block Diagram
MPC860 PowerQUICC UserÕs Manual
U-Bus
Bus Interface
Internal Bus
Dual-Port
RAM
SMC1 SMC2
SDMA
Communications Processor
ROM
MAC
2
SPI I C
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