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Section 19.5.1, ÒRISC Controller ConÞguration Register (RCCR).Ó IDMA and DSP
effectively share the same priority slot; however, within that slot, DSP has priority.
36.10 DSP Event/Mask Registers (SDSR/SDMR)
Since there is no dedicated DSP event register, the CP uses the SDMA status register
(SDSR) to report the maskable DSP interrupts to the core. Figure 36-7 shows the register
format. Note that writing a 1 to the corresponding bits clears the events. SDSR is cleared
by reset and can be read at any time.
Bit
0
Field
SBER
Reset
R/W
Addr
Figure 36-7. DSP Event/Mask Registers (SDSR/SDMR)
Table 36-5 describes the SDSR/SDMR Þelds.
Bits Name
0
SBER SDMA channel bus error. Indicates that an error caused the SDMA channel to be terminated during a
read or write cycle. The SDMA bus error address can be retrieved from the SDMA address register
(SDAR) at internal address (IMMR offset) 0x904.
1Ð5
Ñ
Reserved. Must be cleared.
6
DSP2
DSP chain2 (Tx) interrupt. Set when the current FD in the transmitter chain has been completed.
However, DSP2 only reports if the descriptorÕs I bit is set.
7
DSP1
DSP chain1 (Rx) interrupt. Set when the current FD in the receiver chain has been completed.
However, DSP1 only reports if the descriptorÕs I bit is set.
The SDMA mask register (SDMR) is used to mask the DSP interrupts. SDMR mirrors the
bit format of SDSR. Setting an SDMR bit enables the corresponding interrupt in SDSR;
clearing a bit masks the interrupt. Reset clears SDMR, disabling all interrupts.
36.11 FIR Library Functions
The DSP library provides Þve basic Þnite-impulse response Þlters, each specializing in a
different combination of real or complex coefÞcients, input samples, and output. The
following sections describe each variety of FIR Þlter. Table 36-6 shows the parameter
packet common to all FIR Þlters.
MOTOROLA
1
2
RINT
0x908 (SDSR); 0x90C (SDMR)
Table 36-5. SDSR/SDMR Field Descriptions
Chapter 36. Digital Signal Processing
Part V. The Communications Processor Module
3
4
Ñ
0
R/W
Description
5
6
DSP2
DSP1
7
36-7
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