Motorola MPC860 PowerQUICC User Manual page 215

match is found and the matched entry is valid, then it is a cache hit. If neither tag matches
or the matched tag is not valid, it is a cache miss.
The data path for the instruction cache and its surrounding logic are shown in Figure 8-9.
Data
32
Bypass
Mux
2->1
To Instruction
Sequencer
The 4-word burst buffer holds the last cache block received from the internal bus (the last
miss); the 4-word block buffer holds the last block retrieved from the instruction cache (the
last hit). Note that if one of these buffers contains the requested instruction, it is also
considered a cache hit. To minimize power consumption, the MPC860 can detect that one
of the buffers contains the requested instruction and service the instruction request from the
buffers without activating the instruction cache array.
MOTOROLA
Address [21Ð27]
Address [28Ð29]
Stream
Word
32 128
Select
Mux
4->1
Figure 8-9. Instruction Cache Data Path
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
Set Instruction Cache
Decoder Array
4-Word
128
Cache
Block
Buffer
Hit
Mux
2->1
128
32
128
128
4-Word
Burst
Buffer
Internal Data Bus
8-21