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Part VI. Debug and Test
CLKOUT
0
SRESET
DSDI
CLKEN
DSDI is used after SRESET negation to select clock mode.
If DSDI is slow, the internal asynchronous clock enable signal asserts 8 clocks after SRESET negation.
This enables asynchronous clock mode.
If DSDI is high, self-clocked mode is selected Þrst start bit detected after DSDI negation.
Figure 37-11. Enabling Clock Mode after Reset
Since DSDI is used to select the development port clock scheme, it is necessary to prevent
any transitions on DSDI during clock mode select. The port will not begin scanning for the
start bit of a serial transmission until 16 clocks after the negation of SRESET. If DSDI is
asserted 16 clocks after SRESET negates, the port waits until DSDI is negated to begin
scanning for the start bit.
37.3.2.4 Development Port Serial CommunicationsÐTrap Enable
Mode
When not in debug mode, the development port begins communicating by setting DSDO
(the msb of the 35-bit development port shift register) low to indicate that all activity related
to the previous transmission is complete and that a new transmission can begin. The start
of a serial transmission from an external development tool to the development port is
signaled by a start bit. A mode bit in the transmission deÞnes it as either a trap enable mode
transmission or a debug mode transmission. If the mode bit is set, the transmission will be
10 bits long and only seven data bits will be shifted into the shift register. These seven bits
will be latched into the TECR. A control bit determines whether the data is latched into the
trap enable and VSYNC bits of the TECR or into the breakpoints bits of the TECR.
37.3.2.4.1 Serial Data Into Development Port
The development port shift register is 35 bits wide, but trap enable mode transmissions only
use 10 of the 35 bits as the followingÑthe start/ready bit, a mode/status bit, a control/status
bit, and the 7 least-signiÞcant data bits.
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MOTOROLA
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