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Chapter 9
Memory Management Unit (MMU)
90
90
The MPC860 implements a virtual memory management scheme that provides cache
control, memory access protections, and effective-to-physical (real) address translation.
The MMU largely complies with the PowerPC operating environment architecture (OEA)
with respect to architecturally deÞned memory management features that are appropriate
for this implementation. It does not support some PowerPC MMU features more
appropriate for a personal computer that is expected to run many applications
simultaneously, and in some cases provides greater ßexibility than is deÞnes by the
PowerPC architecture, especially with respect to page sizes. Available protection
granularity is 4-, 16-, 512-Kbyte, or 8-Mbyte pages or 1-Kbyte subpages (for 4-Kbyte
pages only). The MPC860 has separate instruction and data MMUs. The preÞx Mx_
indicates a reference to both the instruction and data (MI_ and MD_) versions of the
register. The MMU supports two protection modesÑPowerPC mode with extended
encoding and domain manager mode, which provides programmable overrides to page
protection settings.
9.1 Features
The following is a list of the MMUÕs important features:
¥ Multiple page sizesÑ4-, 16-, 512-Kbyte, or 8-Mbyte pages (optional 1-Kbyte
subpage protection granularity for 4-Kbyte pages) with the following page
attributes:
Ñ Changed bit support through the DTLB error exception on a write attempt to a
unmodiÞed page (data MMU only)
Ñ Write-through attribute for data accesses.
Ñ Cache-inhibit attribute for data and instruction accesses.
Ñ Default write-through and cache-inhibited attributes can be programmed for
when translation is disabled.
Ñ Guarded attribute for memory-mapped I/O and other nonspeculative regions
¥ Instruction and data address translation can be disabled separately.
¥ MPC860-speciÞc special-purpose registers (SPRs) accessible with the PowerPC
mfspr/mtspr instructions.
MOTOROLA
Chapter 9. Memory Management Unit (MMU)
9-1
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