Motorola MPC860 PowerQUICC User Manual page 976

Part VI. Debug and Test
37.3.2.1 Development Port Pins
The following development port pin functions are provided:
¥ Development serial clock
¥ Development serial data in
¥ Development serial data out
¥ Freeze
37.3.2.1.1 Development Serial Clock (DSCK)
DSCK is used at reset to enable debug mode, which can be entered either immediately
following reset or for event-driven entry into debug mode as described in Section 37.3.1.2,
ÒEntering Debug Mode.Ó The DSCK input must be driven either high or low at all times and
must not be allowed to ßoat. A typical target environment would pull this input low with a
resistor. When the development port is in asynchronous clocked mode, the development
serial clock (DSCK) is used to shift data into and out of the development port shift register.
At the same time, the new msb of the shift register is presented at the DSDO pin.
The clock may be implemented as a free-running or gated clock. As discussed in
Section 37.3.2.4, ÒDevelopment Port Serial CommunicationsÐTrap Enable Mode,Ó and
Section 37.3.2.5, ÒDevelopment Port Serial CommunicationsÐDebug Mode,Ó data shifting
is controlled by the ready and start signals, so the clock does not need to be gated with the
serial transmissions.
37.3.2.1.2 Development Serial Data In (DSDI)
External logic presents data to be transferred into the development port shift register at the
development serial data in pin (DSDI). When driven asynchronously with the system clock,
data presented to DSDI must be stable at setup time before the rising edge of DSCK and at
hold time after the rising edge of DSCK. When driven synchronously to the system clock,
data must be stable on DSDI or a setup time before system clock output (CLKOUT) rising
edge and a hold time after the rising edge of CLKOUT. DSDI is also used at reset to select
the development port clock mode. See Section 37.3.2.3, ÒDevelopment Port Serial
CommunicationsÐClock Mode.Ó
37.3.2.1.3 Development Serial Data Out (DSDO)
Debug mode logic uses the development serial data out pin (DSDO) to shift data out of the
development port shift register. DSDO transitions are synchronous with DSCK or
CLKOUT, depending on the clock mode.
37.3.2.1.4 Freeze
The freeze indication means that the processor is in debug mode (normal processor
execution of user code is frozen). Freeze state is indicated on FRZ and is generated
synchronously to the system clock. This indication can be used to halt any off-chip device
while in debug mode and is a handshake between the debug tool and port. In addition to
FRZ, the freeze state is indicated by the value 0b11 on VFLS[0Ð1], shown in Figure 37-8.
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