Part IV. Hardware Interface
CS1
DRAM
BS[0Ð3]
Bank
GPL_A5
Multiplexer
BADDR[28Ð30]
A[6Ð31]
D[0Ð31]
R/W
TS
BURST
External
MPC860
TA
Master
TSIZ[0Ð1]
BI
BR
BG
BB
Figure 16-49. Synchronous External Master Interconnect Example
MOTOROLA
Chapter 16. Memory Controller
16-55