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Numerics
860, see MPC860
A
Accessing HDLC bus, 24-19
Acronyms and abbreviated terms, list, lxx, lxxvi,
xix, x, xv, xxx, xxxvi
Alignment
aligned accesses, 6-1
alignment on transfers, 14-23
An (address bus) signals, 3-3, 13-5, 14-3, 14-30
AS (address strobe) signal, 3-11, 13-14
Asynchronous HDLC mode
channel implementation, 26-5
configuring GSMR/DSR, 26-6
frame transmission processing, 26-2
ATn (address type) signals, 14-4, 14-30
Auto-buffering, 20-12
B
BADDRn (burst address) signal, 3-10, 13-14
Baud rate generator clock (BRGCLK), 15-14
Baud
rate
generator
register, 21-40
BB (bus busy) signal, 3-6, 13-8, 14-6, 14-27
BDIP
(burst
signal, 3-4, 13-5, 14-4, 14-33
BDLE (SCC BISYNC DLE) register, 27-8
BG (bus grant) signal, 3-6, 13-8, 14-6, 14-26
BI (burst inhibit) signal, 3-4, 13-6, 14-5, 14-33
Big-endian (BE) mode, A-2
Block diagram, 860, 4-4
Block diagrams
CPM timer, 18-5
Boot chip-select operation, 16-27
Boundedly undefined, definition, 6-4
BR (bus request) signal, 3-6, 13-8, 14-6, 14-26
Branch folding timing, 10-4
Branch instructions
branch instructions, D-24
condition register logical, D-24
system linkage, D-25
trap, D-25
Branch prediction timing, 10-5
Break support (UART receiver), 23-9
Breakpoint
counters, 37-14
debug support, 37-8
features list, 37-9
load/store example, 37-18
operation details, 37-15
Breakpoint address (BAR) register, 37-38
Breakpoint counter value and control
MOTOROLA
configuration
(BRGC)
data
in
progress)
INDEX
(COUNTA/COUNTB) registers, 37-43
BRn (base registers), 16-8
BS_An (byte select) signals, 3-7, 13-9
BSYNC (BISYNC SYNC) register, 27-7
Buffer-chaining, 20-12
BURST (burst transfer) signal, 3-3, 13-5, 14-4, 14-30
Burst bus operations, 14-14
Burst transfer bus operation, 14-13
Bus arbitration, 14-25
Bus exception control cycles, 14-37
Bus interface
accessing HDLC bus, 24-19
bus utilization, B-2
hierarchical bus interface example, 16-51
system bus performance, B-2
Bus interface, external
address bus, 14-30
address type, 14-30
arbitration phase, 14-25
burst data in progress, 14-33
burst indicator, 14-30
burst inhibit, 14-33
bus busy, 14-27
bus exception control cycles, 14-37
bus grant, 14-26
bus operations, 14-6
bus request, 14-26
control signals, 14-2
features summary, 14-1
program trace, 14-30
read/write, 14-30
reservation transfer, 14-30
retry, 14-38
signal descriptions, 14-2
storage reservation, 14-34
transfer acknowledge, 14-33
transfer error acknowledge, 14-33
transfer signals, 14-1
transfer size, 14-30
transfer start, 14-29
Bus operations
burst operations, 14-14
burst transfer, 14-13
single-beat read flow, 14-7
single-beat transfer, 14-7
single-beat write flow, 14-9
transfer protocol, 14-6
BYPASS instruction, 38-7
Byte ordering
BE (big-endian) mode, A-2
mechanisms, A-1
overview, A-1
PPC-LE (PowerPC little-endian) mode, A-6
TLE (true little-endian) mode, A-2
Byte stuffing, 27-1
Index
Index--1
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