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Part V. The Communications Processor Module
33.3.1.1 PIP Function Code Register (PFCR)
Figure 33-2 shows the PIP function code register (PFCR).
Bit
0
Field
Reset
R/W
Addr
Figure 33-2. PIP Function Code Register (PFCR)
Table 33-2 describes the PFCR Þelds.
Bits
Name
0Ð2 Ñ
Reserved and should be 0.
3Ð4 BO
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy, it
takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning
of the next BD. See Appendix A, ÒByte Ordering.Ó
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5Ð7 AT[1Ð3] Address type 1Ð3. Contains the user-deÞned function code value used during the SDMA channel
memory access. AT0 is always driven high to identify this channel access as a DMA-type access.
33.3.1.2 Status Mask Register (SMASK)
The status mask register (SMASK), shown in Figure 33-3, is important only if the PIP is
implementing a Centronics-type transmitter and the CP controls the transfer; see
Section 33.9, ÒImplementing Centronics.Ó When the CP is handling the DMA transfers, it
automatically checks the status lines (from a printer) and masks them against SMASK.
Unmasked signals are ßagged as errors in the TxBD; see Section 33.5.1, ÒThe PIP Tx
Buffer Descriptor (TxBD).Ó
If the core controls the transmitter, the masking function can be performed in software by
reading the individual status signals for errors. When receiving, core software drives the
status signals using general-purpose outputs.
Bit
0
Field
R/W
Addr
33-4
1
2
Ñ
0000_0000_0000_0000
Table 33-2. PFCR Field Descriptions
1
2
0
Figure 33-3. Status Mask Register (SMASK)
MPC860 PowerQUICC UserÕs Manual
3
4
BO
R/W
PIP base + 0x04
Description
3
4
F
R/W
PIP base + 0x05
5
6
AT[1Ð3]
5
6
PE
S
MOTOROLA
7
7
0
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