Motorola MPC860 PowerQUICC User Manual page 425

Table 15-9. PLPRCR Field Descriptions (Continued)
Bits Name
19 TMIST Timers interrupt status. Cleared at reset. Set when a real-time clock, periodic interrupt timer,
timebase, or decrementer interrupt occurs. This bit is cleared by writing a 1 (writing a zero has no
effect). Entry into low-power mode is disabled when TMIST is set.
0 = No timer interrupt was detected.
1 = A timer interrupt was detected.
20 Ñ Reserved, should be cleared.
21 CSRC Clock source. SpeciÞes whether DFNH or DFNL generates the general system clock. Cleared by
hard reset.
0 = The general system clock is generated by the DFNH Þeld.
1 = The general system clock is generated by the DFNL Þeld.
22Ð23 LPM Low-power modes. This bit, in conjunction with TEXPS and CSRC, speciÞes the operating mode of
the core. There are seven possible modes. In the normal modes, you can write a non-zero value to
this Þeld. In the other modes, only a reset or asynchronous interrupt can clear this Þeld.
00 = Normal high/normal low mode.
01 = Doze high/doze low mode.
10 = Sleep mode.
11 = Deep-sleep/power-down mode.
24 CSR Checkstop reset enable. Enables an automatic reset when the processor enters checkstop mode. If
the processor enters debug mode at reset, then reset is not generated automatically; refer to
Table 15-10. See Section 37.5.2.2, ÒDebug Enable Register (DER).Ó
25 LOLRE Loss-of-lock reset enable. Enables hard reset generation when a loss-of-lock indication occurs.
0 =A hard reset is not generated when a loss-of-lock is indicated.
1 =A hard reset is generated when a loss-of-lock is indicated.
26 FIOPD Force I/O pull down. Indicates when the address and data external pins are driven by an internal
pull-down device in sleep and deep-sleep mode.
0 =No pull-down on the address and data bus.
1 =Address and data bus is driven low in sleep and deep-sleep mode.
27Ð31 Ñ Reserved, should be cleared.
Table 15-10 describes PLPRCR[CSR] and DER[CHSTPE] bit combinations.
Table 15-10. PLPRCR[CSR] and DER[CHSTPE] Bit Combinations
PLPRCR[CSR]
0
0
0
0
1
1
1
1
MOTOROLA
DER[CHSTPE] Checkstop Mode
0
0 Yes
1
1 Yes
0
0 Yes
1
1 Yes
Chapter 15. Clocks and Power Control
Description
No
No
Enter debug mode
No
Automatic reset
No
Enter debug mode
Part IV. Hardware Interface
Result
Ñ
Ñ
Ñ
Ñ
Ñ
15-31