Motorola MPC860 PowerQUICC User Manual page 454

Part IV. Hardware Interface
Table 16-12. Boot Bank Field Values after Reset
Register
BR0
OR0
16.5.3 External Asynchronous Master Support
Figure 16-29 shows the basic interface between an asynchronous external master and the
GPCM to allow connection to static RAM.
Figure 16-29. Asynchronous External Master Configuration for GPCM-Handled
Figure 16-30 shows the timing for TRLX = 0 when an external asynchronous master
accesses SRAM. TA, WE, and OE remain asserted until the external master negates AS, at
which point they deassert asynchronously.
16-28
Field
PS From hard reset conÞguration word
PARE 0
WP 0
MS[0Ð11] 00
V From hard reset conÞguration word
AM[0Ð16] All zeros
ATM[0Ð2] 000
CSNT 1
ACS[0Ð1] 11
BIH 1
SCY[0Ð3] 1111
SETA 0
TRLX 1
EHTR 0
ASYNCHRONOUS EXTERNAL MASTER
TA AS Address Data
MPC860
TA
AS
Address
CS
OE
WE
Data
Memory Devices
MPC860 PowerQUICC UserÕs Manual
Value
MEMORY
Address
CE
OE
W
Data
MOTOROLA