Motorola MPC860 PowerQUICC User Manual page 1009

MSR[LE]=0
MSR[ILE]=0
For TLE mode, MSR[LE] and MSR[ILE] should be cleared as in BE mode. (This disables
the 3-bit address munging used in PPC-LE mode. See Section A.5, ÒPPC-LE Mode,Ó for
more information.)
For TLE mode, DC_CST[LES] should be set. When DC_CST[LES] is set, the physical
address is modiÞed before the data cache or load/store unit accesses the internal U-bus. The
two low-order address bits of the effective address are exclusive-ORed (XOR) with a
two-bit value that depends on the length of the operand (1, 2, or 4 bytes), as shown in
Table A-2. This process is called 2-bit munging.Õ
Since all instructions are 4 byte words, no address modiÞcations by the instruction cache
are necessary.
MOTOROLA
PowerPC Core
I-Cache D-Cache
2-Bit Munge
DC_CST[LES]=1
U-Bus
SDMA
FCR[BO]=1x
CPM
Figure A-1. TLE Mode Mechanisms
Table A-2. TLE 2-bit Munging
Data Width (Bytes)
4
2
1
Appendix A. Byte Ordering
MPC860
SIU
2-Bit UnMunge
and Byte Swap
for Accesses
Initiated by the
PowerPC Core
DC_CST[LES]=1
Address ModiÞcation
No change
XOR with 0b10
XOR with 0b11
Appendixes
External bus
A-3