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Part IV. Hardware Interface
Table 14-1. MPC860 Signal Overview (Continued)
Signal
Pins Active I/O
BURST
1
Low
Burst
Transfer
TSIZ[0Ð1]
2
High
Transfer Size
AT[0Ð3]
4
High
Address Type
RSV
1
Low
Reservation
Transfer
PTR
1
High
Program
Trace
BDIP
1
Low
Burst Data in
Progress
TS
1
Low
Transfer Start
STS
1
Low
Special
Transfer Start
CR
1
Low
Cancel
Reservation
KR/RETRY
1
Low
Kill
Reservation/
Retry
14-4
O
Driven by the MPC860 along with the address when it owns the external bus.
Driven low indicates that a burst transfer is in progress. Driven high indicates that
the current transfer is not a burst.
I
Sampled by the MPC860 when an external device initiates a transaction and the
memory controller was conÞgured to handle external master accesses.
O
Driven by the MPC860 along with the address when it owns the external bus.
SpeciÞes the data transfer size for the transaction.
I
Sampled by the MPC860 when an external device initiates a transaction and the
memory controller was conÞgured to handle external master accesses.
O
Driven by the MPC860 along with the address when it owns the external bus.
Indicates additional information about the address on the current transaction.
O
Driven by the MPC860 along with the address when it owns the external bus.
Indicates additional information about the address on the current transaction.
O
Driven by the MPC860 along with the address when it owns the external bus.
Indicates additional information about the address on the current transaction.
O
Driven by the MPC860 when it owns the external bus as part of the burst protocol.
Asserted indicates that the second beat in front of the current one is requested by
the master. Negated before the burst transfer ends to abort the burst data phase.
Transfer Start
O
Driven by the MPC860 when it owns the external bus. Indicates the start of a
transaction on the external bus.
I
Sampled by the MPC860 when an external device initiates a transaction and the
memory controller was conÞgured to handle external master accesses.
O
Driven by the MPC860 when it owns the external bus. Indicates the start of a
transaction on the external bus or signals the beginning of an internal transaction
in show cycle mode.
Reservation Protocol
I
Point-to-point signal from external snoop logic. Asserted: tells the bus master to
clear its reservation because another device touched its reserved space. This is a
pulsed signal.
I
If the core initiates a bus cycle by executing a stwcx. to a nonlocal bus on which
the memory reservation is lost, the nonlocal bus uses this signal to back-off the
cycle. See Section 14.4.9, ÒMemory Reservation.Ó
For regular transactions, the slave device drives this signal to indicate that the
MPC860 must relinquish the bus and retry the cycle.
MPC860 PowerQUICC UserÕs Manual
Description
MOTOROLA
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