Motorola MPC860 PowerQUICC User Manual page 232

Part II. PowerPC Microprocessor Module
MSR[PR] M_CASID[CASID]
32-Entry Fully Associative TLB
Translation
Enabled
32-Bit Physical Address
Figure 9-3. Effective-to-Physical Address Translation for 4-Kbyte Pages Block
A TLB hit occurs if the incoming EA matches the EPN and M_CASID[CASID] matches
the ASID Þeld in a valid TLB entry, and if the subpage validity ßag is set for the subpage
that the incoming EA points to. If a hit is detected, the contents of the physical page number
are concatenated with the appropriate number of lsbs from the EA to form the physical
address sent to the cache and memory system.
9.4 Using Access Protection Groups
Access control is assigned on a page-by-page basis; additional control is provided on a
protection group basis. Each TLB entry holds an access protection group (APG) number.
When a match is detected, the value of the matched entryÕs APG is used to index a Þeld in
the access protection register (MI_AP or MD_AP) that deÞnes access control for the
translation. Each Mx_AP contains 16 Þelds. The Þeld content is used according to the group
protection mode.
To be consistent with the PowerPC OEA, the APG value should match the four msbs of the
effective page number. To override protection using APG, use it on blocks of addresses
which are deÞned by the 4 msbs of the effective page number. If APG is not to be used for
a particular block, set the GP for that block to ÔclientÕ in the Mx_AP register. To ignore it
globally, set all of the Mx_AP Þelds to 01. In PowerPC mode, each Þeld holds the Kp and
Ks bits for the corresponding segment deÞned by the level-one table descriptor. In domain
manager mode, each Þeld holds override information over the page protection settingÑno
override, no access override, and free access override.
9-6
32-Bit EA
20-Bit
Page Byte
20-Bit 12-Bit
20-Bit
Physical Page Number Byte
Translation
Enabled
Diagram
MPC860 PowerQUICC UserÕs Manual
32-Bit Logical
Address
Page Protection
Free Access
Protection
Group Number
No Access
Protection
Lookup Table
Implementation-
SpeciÞc TLB
Miss Exceptions
to Core
Implementation-
SpeciÞc
Error Exceptions
to Core
Exception
Logic
MOTOROLA