Motorola MPC860 PowerQUICC User Manual page 1026

Appendixes
C.2 PowerPC RegistersÑSupervisor Registers
All supervisor-level registers implemented on the
register (MSR), described in Table C-3
Table C-3. Supervisor-Level PowerPC Registers
Description
Machine state register
Table C-4 lists supervisor-level SPRs defined by the PowerPC architecture.
SPR Number
Decimal SPR[5Ð9] SPR[0Ð4]
18 00000 10010
19 00000 10011
22 00000 10110
26 00000 11010
27 00000 11011
272 01000 10000
273 01000 10001
274 01000 10010
275 01000 10011
284 01000 11100
285 01000 11101
287 01000 11111
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.
C.3 MPC860-SpeciÞc SPRs
Table C-2 and Table C-5 list SPRs speciÞc to the MPC860. Debug registers, which have
additional protection, are described in Chapter 37, ÒSystem Development and Debugging.Ó
C-2
.
Name
MSR See Section 5.1.2.3.1, ÒMachine State Register
(MSR).Ó
Table C-4. Supervisor-Level PowerPC SPRs
Name
DSISR See the Programming Environments
Manual and Section 5.1.2.1, ÒDAR,
DSISR, and BAR Operation.Ó
DAR See the Programming Environments
Manual and Section 5.1.2.1, ÒDAR,
DSISR, and BAR Operation.Ó
DEC See Section 11.8.1, ÒDecrementer
Register (DEC),Ó and in Chapter 15,
ÒClocks and Power ControlÓ
SRR0 See SRR0 settings for individual
exceptions in Chapter 7, ÒExceptions.Ó
SRR1 See SRR1 settings for individual
exceptions in Chapter 7, ÒExceptions.Ó
SPRG0 See the Programming Environments
Manual.
SPRG1
SPRG2
SPRG3
1
TBL write See Section 11.9, ÒThe PowerPC
Timebase
1
TBU write
and Power Control.Ó
PVR Section 5.1.2.3.2, ÒProcessor Version
Register.Ó
MPC860 PowerQUICC UserÕs Manual
MPC860
are SPRs, except for the machine state
Comments
Comments
,Ó
and Chapter 15, ÒClocks
Serialize Access
Write fetch sync
Serialize Access
Write: Full sync
Read: Sync relative to
load/store operations
Write: Full sync
Read: Sync relative to load/
store operations
Write
Write
Write
Write
Write (as a store)
No (read-only register)
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