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PCDIR and PCPAR bits are cleared at system reset, making all port signals general-purpose
inputs. The CPM interrupt mask register (CIMR) (see Section 35.5.3, ÒCPM Interrupt
Mask RegisterÓ) is also cleared, so port C I/O signals left ßoating do not cause false
interrupts.
General-purpose port C I/O signals can be accessed through PCDAT where written data is
stored in an output latch. If a port C signal is conÞgured as an output, output latch data is
gated onto the port signal. Reading PCDAT reads the value of the port signal itself. For port
C input signals, data written to PCDAT is stored in the output latch but cannot reach the
port signal. In this case, when the PCDAT register is read, the state of the port signal is read.
The following steps conÞgure port C signals as general-purpose outputs. When the signal
is conÞgured as an output, port C interrupts are not generated.
1. Write the corresponding PCPAR bit with a 0.
2. Write the corresponding PCDIR bit with a 1.
3. Write the corresponding PCSO bit with a zero (for clarity).
4. The corresponding PCINT bit is a ÔdonÕt careÕ.
5. Write the signal value using the PCDAT register.
The following steps can be taken to conÞgure a port C signal as a general-purpose input
signal that does not generate an interrupt:
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a zero.
3. Write the corresponding PCSO bit with a zero.
4. The corresponding PCINT bit is a ÔdonÕt careÕ bit.
5. Write the corresponding CIMR bit with a zero to prevent interrupts from being
generated to the core.
6. Read the signal value using the PCDAT register.
When a port C signal is conÞgured as a general-purpose I/O input, a change in the port C
interrupt register (PCINT) causes an interrupt request signal to be sent to the CPIC. Each
port C signal can be conÞgured to assert an interrupt request either when a high-to-low
change occurs or when any change occurs. Each port C signal asserts a unique interrupt
request to the CPM interrupt pending register (CIPM) (see Section 35.5.2, ÒCPM Interrupt
Pending Register (CIPR)Ó) and has a different internal interrupt priority level within the
CPM interrupt controller (see Section 35.2, ÒCPM Interrupt Source Priorities.Ó
Requests can be masked independently in the CPM interrupt mask register (CPMR). See
Section 35.5.3, ÒCPM Interrupt Mask Register.Ó The following steps conÞgure a port C
signal as a general-purpose input that generates an interrupt:
1. Write the corresponding PCPAR bit with a 0.
2. Write the corresponding PCDIR bit with a 0.
MOTOROLA
Part V. The Communications Processor Module
Chapter 34. Parallel I/O Ports
34-13
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