Motorola MPC860 PowerQUICC User Manual page 494

Part IV. Hardware Interface
CLKOUT/GCLK2_50
GCLK1_50
TA
CS1 (RAS)
BS_A[0Ð3] (CAS[0Ð3])
cst4 Bit 0
cst1 Bit 1
cst2 Bit 2
cst3 Bit 3
bst4 Bit 4
bst1 Bit 5
bst2 Bit 6
bst3 Bit 7
g0l0 Bit 8
g0l1 Bit 9
g0h0 Bit 10
g0h1 Bit 11
g1t4 Bit 12
g1t3 Bit 13
g2t4 Bit 14
g2t3 Bit 15
g3t4 Bit 16
g3t3 Bit 17
g4t4 Bit 18
g4t3 Bit 19
g5t4 Bit 20
g5t3 Bit 21
Ð Bit 22
Ð Bit 23
loop Bit 24
exen Bit 25
amx0 Bit 26
amx1 Bit 27
na Bit 28
uta Bit 29
todt Bit 30
last Bit 31
Page read accesses can be improved signiÞcantly by setting MAMR[GPLA4DIS] and
ignoring GPL_A4. The processor samples the data bus at the falling edge of GCLK2_50
when TA is asserted. Figure 16-62 shows how to use this feature to change the burst read
access to page mode DRAM (no loop). During the four consecutive data beats, TA is
asserted to ensure a data transfer on every data clock. The Þgure also shows how the burst
read access shown in Figure 16-56 of can be reduced from 9 to 6 cycles (for 32-bit port
size). Cycles can be reduced by using faster DRAM or a slower system clock that meets the
DRAM access time. For a 16-bit port size memory, the reduction is from 17 to 10 cycles
and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles.
16-68
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
EXS
Figure 16-61. Exception Cycle
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