Motorola MPC860 PowerQUICC User Manual page 872

Part V. The Communications Processor Module
¥ The word at offset + 4 points to the beginning of the buffer.
Ñ For an RxBD, the value must be even and can reside in internal or external
memory.
Ñ For a TxBD, this pointer can be even or odd, unless the port size exceeds 8 bits,
for which it must be even. The buffer can reside in internal or external memory.
33.5.1 The PIP Tx Buffer Descriptor (TxBD)
The CP uses buffer descriptors (TxBDs) to conÞrm buffer transmission and indicate error
conditions to the core. Figure 33-9 shows the PIP TxBD.
0 1
Offset + 0 R Ñ
Offset + 2
Offset + 4
Offset + 6
Table 33-9 describes the PIP Tx buffer descriptor status and control Þeld. The data length
and buffer pointer are described in Section 33.5, ÒPIP Buffer Descriptors,Ó above.
Table 33-9. PIP TxBD Status and Control Field Descriptions
Bits Name
0 R Ready. If PIP tries to transmit a buffer that is not ready, PIPE[TXE] is ßagged.
0 The buffer associated with this descriptor is not ready for transmission. This descriptor and its buffer
can be updated. The CP clears R after the buffer is sent or an error is encountered.
1 The buffer is ready for sending or is being sent. No Þelds of this BD can be written while R = 1.
1 Ñ Reserved and should be cleared.
2 W Wrap (last buffer descriptor in TxBD table). The number of TxBDs in the table is determined only by
the W bit and space constraints of the dual-port RAM.
0Not the last descriptor in the TxBD table.
1 The last BD in the TxBD table. After this BD is processed, the current TxBD pointer wraps to the top
of the TxBD table (TBASE).
3 I Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 PIPE[TXB] is set when this buffer is serviced by the CP, which can cause an interrupt.
4 L Last.
0 Not the last buffer of the frame.
1 Last buffer of the frame.
5 Ñ Reserved and should be cleared.
6 CM Continuous mode.
0 Normal operation.
1 The CP does not clear R after this buffer is closed, allowing the associated buffer to be resent when
the CP next accesses this BD. However, R is cleared if an error occurs during transmission.
7Ð11 Ñ Reserved and should be cleared.
33-12
2 3 4 5
W I L Ñ CM
Figure 33-9. PIP Tx Buffer Descriptor (TxBD)
MPC860 PowerQUICC UserÕs Manual
6 7 8 9 10
Ñ
Data Length
Tx Buffer Pointer
Description
11 12 13 14 15
F PE S
MOTOROLA
Ñ