Motorola MPC860 PowerQUICC User Manual page 916

Part V. The Communications Processor Module
36.2 DSP Functionality
DSP functionality can be divided into three layersÑhardware, Þrmware and software; see
Figure 36-1.
Figure 36-1. DSP Functionality Implementation
The user deÞnes the software layer to build an application. A software interface is deÞned
that enables parameters (pointer to Þlter coefÞcients, and pointers to input and output
buffers) to be passed between the core and the CPM. Several functions can be chained
together to reduce core intervention and interrupt rates, assuming that all data structures are
in the dual-port RAM. Two special DSP host commands signal the CPM to initialize or to
execute the DSP FD chain. A maskable interrupt signals the core to resume control once
the CPM executes the chain.
Table 36-1 lists the available DSP functions with opcodes.
Function Opcode
FIR1 00001
FIR2 00010
FIR3 00011
FIR5 00101
FIR6 00110
IIR 00111
MOD 01000
DEMOD 01001
LMS1 01010
LMS2 01011
WADD 01100
36-2
Core Software
CPM Firmware
CPM Hardware
Table 36-1. DSP Library Functions
Input CoefÞcient
Real Real
Complex Real
Complex Complex
Complex Complex
Real Complex
Real Real
Complex Complex
Real Complex
Ñ Ñ
Ñ Ñ
Real Ñ
MPC860 PowerQUICC UserÕs Manual
Function descriptor chain in external
memory deÞnes the sequence and data
ßow of the DSP functions.
Generic DSP microcode routine library
stored in the internal ROM.
MAC and address generator modules
in the CP architecture.
Output
Real Decimation, Rx interpolation
Complex Tx Þlter, Rx Þlter
Real/Complex EC computation, equalizer
Real/Complex Fractionally spaced equalizer
Complex Ñ
Real Biquad Þlter
Real/Complex Tx modulation
Complex Rx demodulation
Ñ EC update, equalizer update (T/2, T/3)
Ñ Equalizer update (2T/3)
Real Interpolation
Application
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