Motorola MPC860 PowerQUICC User Manual page 332

Part IV. Hardware Interface
Name Reset
TA Hi-Z
TEA Hi-Z
BI Hi-Z
RSV See
IRQ2 Section
13.5
KR/RETRY See
IRQ4 Section
SPKROUT 13.5
CR Hi-Z
IRQ3
13-6
Table 13-1. Signal Descriptions (Continued)
Number Type
C2 Bidirectional
Active
Pull-up
D1 Open-drain Transfer Error AcknowledgeÑIndicates that a bus error
E3 Bidirectional
Active
Pull-up
H3 Bidirectional
Three-state
K1 Bidirectional
Three-state
F2 Input
MPC860 PowerQUICC UserÕs Manual
Description
Transfer AcknowledgeÑIndicates that the slave device
addressed in the current transaction accepted data sent by the
master (write) or has driven the data bus with valid data (read).
This is an output when the PCMCIA interface or memory
controller controls the transaction. The only exception occurs
when the memory controller controls the slave access by
means of the GPCM and the corresponding option register is
instructed to wait for an external assertion of TA. Every slave
device should negate TA after a transaction ends and
immediately three-state it to avoid bus contention if a new
transfer is initiated addressing other slave devices. TA requires
the use of an external pull-up resistor.
occurred in the current transaction. The MPC860 asserts TEA
when the bus monitor does not detect a bus cycle termination
within a reasonable amount of time. Asserting TEA terminates
the bus cycle, thus ignoring the state of TA. TEA requires the
use of an external pull-up resistor.
Burst InhibitÑIndicates that the slave device addressed in the
current burst transaction cannot support burst transfers. It acts
as an output when the PCMCIA interface or the memory
controller takes control of the transaction. BI requires the use
of an external pull-up resistor.
ReservationÑThe MPC860 outputs this three-state signal in
conjunction with the address bus to indicate that the core
initiated a transfer as a result of a stwcx. or lwarx.
Interrupt Request 2ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
Kill ReservationÑInput used as a part of the memory
reservation protocol, when the MPC860 initiated a transaction
as the result of a stwcx. instruction.
RetryÑInput used by a slave device to indicate it cannot
accept the transaction. The MPC860 must relinquish
mastership and reinitiate the transaction after winning in the
bus arbitration.
Interrupt Request 4. One of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. Note that the interrupt request signal
that is sent to the interrupt controller is the logical AND of this
line (if deÞned as IRQ4) and DP1/IRQ4 (if deÞned as IRQ4).
SPKROUTÑDigital audio wave form output to be driven to the
system speaker.
Cancel ReservationÑInput used as a part of the storage
reservation protocol.
Interrupt Request 3ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. Note that the interrupt request signal
sent to the interrupt controller is the logical AND of CR/IRQ3 (if
deÞned as IRQ3) and DP0/IRQ3 if deÞned as IRQ3.
MOTOROLA