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Part IV. Hardware Interface
Bits
Name
5
CABVD2_C
6
CABVD1_C
7
8
CARDY_L
9
CARDY_H
10
CARDY_R
11
CARDY_F
12Ð15
16
CBVS1_C
17
CBVS2_C
18
CBWP_C
19
CBCD2_C
20
CBCD1_C
21
CBBVD2_C
22
CBBVD1_C
23
24
CBRDY_L
25
CBRDY_H
26
CBRDY_R
27
CBRDY_F
28Ð31
17.4.3 PCMCIA Interface Enable Register (PER)
Setting a bit in the PER, shown in Figure 17-5, enables the corresponding interrupt.
Bit
0
1
Field CA
EVS1 CA
EVS2 CA
_
_
Reset
R/W
Addr
Bit
16
17
Field CB
EVS1 CB
EVS2 CB
_
_
Reset
R/W
Addr
17-10
Table 17-9. PSCR Field Descriptions (Continued)
Battery voltage/SPKR in for card A changed
Battery voltage/STSCHG in for card A changed
Ñ
Reserved, should be cleared.
RDY/IRQ of card A pin is low. Device and socket interrupt.
RDY/IRQ of card A pin is high. Device and socket interrupt.
RDY/IRQ of card A pin rising edge detected. Device and socket interrupt.
RDY/IRQ of card A pin falling edge detected. Device and socket interrupt.
Ñ
Reserved, should be cleared.
Voltage sense 1 for card B changed
Voltage sense 2 for card B changed
Write Protect for card B changed
Card detect 2 for card B changed
Card detect 1 for card B changed
Battery voltage/SPKR in for card B changed
Battery voltage/STSCHG in for card B changed
Ñ
Reserved, should be cleared.
RDY/IRQ of card B pin is low. Device and socket interrupt.
RDY/IRQ of card B pin is high. Device and socket interrupt.
RDY/IRQ of card B pin rising edge detected. Device and socket interrupt.
RDY/IRQ of card B pin falling edge detected. Device and socket interrupt.
Ñ
Reserved, should be cleared.
2
3
4
EWP CA
ECD2 CA
ECD1 CA
_
_
_
18
19
20
EWP CB
ECD2 CB
ECD1 CB
_
_
_
Figure 17-5. PCMCIA Interface Enable Register (PER)
MPC860 PowerQUICC UserÕs Manual
Description
5
6
7
EBVD2 CA
EBVD1 Ñ CA
_
_
0000_0000_0000_0000
R/W
(IMMR & 0xFFFF0000) + 0x0F8
21
22
23
EBVD2 CB
EBVD1 Ñ CB
_
_
0000_0000_0000_0000
R/W
(IMMR & 0xFFFF0000) + 0x0FA
8
9
10
ERDY
L CA
ERDY
H CA
ERDY
_
_
_
_
_
24
25
26
ERDY
L CB
ERDY
H CB
ERDY
_
_
_
_
_
11
12-15
R CA
ERDY
F Ñ
_
_
_
27
28-31
R CB
ERDY
F Ñ
_
_
_
MOTOROLA
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