Motorola MPC860 PowerQUICC User Manual page 1090

DEC (decrementer) register, 11-23
Decrementer, 11-23
Development port data register (DPDR), 37-47
Development port shift register, 37-27
Development support
programming model, 37-36
Development system interface
checkstop state and debug mode, 37-24
debug mode operation, 37-21
development port communication, 37-25
fast download procedure, 37-34
freeze indication, 37-26
overview, 37-19
registers, 37-27
signals, 37-26
Digital phase-locked loop (DPLL) operation, 22-22
Digital signal processing (DSP)
CP commands, 36-6
CPM function priority, 36-6
CPM performance calculation, 36-33
data representation, 36-4
DEMOD, 36-23
features, 36-1
FIR library functions, 36-7
function descriptors, 36-3
function execution times, 36-33
functionality, 36-2
input/output buffers, 36-5
LMS1, 36-25
LMS2, 36-26
modulation (MOD), 36-21
overview, 36-1
parameter RAM, 36-5
performance comparison (core vs. CPM), 36-30
weighted vector addition (WADD), 36-28
DMA module, 17-7
Dn (data bus) signals, 3-5, 13-7, 14-5
DPn (parity bus) signals, 3-5, 13-7, 14-5
DSR (data synchronization register), 22-10, 23-11
DSR (data synchronization register) (asynchronous
HDLC), 26-7
E
Effective address calculation, 6-6
Endian modes
BE mode, A-2
PPC-LE mode, A-6
setting endian modes, A-8
TLE mode, A-2
Exceptions
alignment exception, 7-7
asynchronous exceptions, 7-3
breakpoint detection, 37-8
bus exception control cycles, 14-37
Index--4
INDEX
Execution synchronization, 6-7
External bus interface, see Bus interface, external
External control instructions, D-26
External load timing, 10-3
External test (EXTEST) instruction, 38-6
F
Features
Features lists
MPC860 PowerQUICC UserÕs Manual
debug exceptions, 7-15
decrementer exception, 7-10
DSI exception, 7-6
DTLB error, 7-14, 9-32
DTLB miss, 7-13, 9-32
exception handling, 7-1, 16-43
exception latency, 7-18
exception priority, 7-4
external interrupt, 7-6
external reset exception, 20-22
floating-point assist, 7-12
instruction offset, 7-2
instruction-related exceptions, 6-7
integer alignment, 7-8
ISI exception, 7-6
ITLB error, 7-13, 9-32
ITLB miss, 7-12, 9-32
list of exceptions, 7-2
machine check interrupt, 7-5
MMU exceptions, 9-32
ordering, 7-3
partially completed instructions, 7-19
PCMCIA interrupts, 17-6
PowerPC defined, 7-4
precise exception model, implementing, 7-16
program exception, 7-9
recoverability after an exception, 7-17
RISC timer interrupt handling, 19-17
SCC interrupt handling, 22-16
software emulation, 7-12
synchronous exceptions, 7-3
system call, 7-10
system reset interrupt, 7-5
trace exception, 7-11
breakpoint debug support, 37-9
DSP features, 36-1
SCC UART mode, 23-2
watchpoint debug support, 37-9
AppleTalk mode, 25-2
asynchronous HDLC mode, 26-1
BISYNC mode, 27-2
clocks and power control, 15-1
communications processor, 19-1
CPIC, 35-1
CPM features, 18-1
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