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Changed bit. One of two page history bits found in each page table entry
Clear. To cause a bit or bit Þeld to register a value of zero. The opposite of set.
Context synchronization. An operation that ensures that all instructions in
Copy-back. An operation in which modiÞed data in a cache block is copied
Critical-data Þrst. An aspect of burst accesses that allow the requested data
D
Denormalized number. A nonzero ßoating-point number whose exponent
Direct-mapped cache. A cache in which each main memory address can
Direct-store. Interface available on PowerPC processors only to support
E
Effective address (EA). The 32- or 64-bit address speciÞed for a load, store,
Exception. A condition encountered by the processor that requires special,
MOTOROLA
(PTE). The processor sets the changed bit if any store is performed
into the page. See also Page access history bits and Referenced bit.
execution complete past the point where they can produce an
exception, that all instructions in execution complete in the context
in which they began execution, and that all subsequent instructions
are fetched and executed in the new context. Context synchronization
may result from executing speciÞc instructions (such as isync or rÞ)
or when certain events occur (such as an exception).
back to memory.
(typically a word or double word) in a cache block to be transferred
Þrst.
has a reserved value, usually the format's minimum, and whose
explicit or implicit leading signiÞcand bit is zero.
appear in only one location within the cache, operates more quickly
when the memory request is a cache hit.
direct-store devices from the POWER architecture. When the T bit
of a segment descriptor is set, the descriptor deÞnes the region of
memory that is to be used as a direct-store segment. Note that this
facility is being phased out of the architecture and will not likely be
supported in future devices. Therefore, software should not depend
on it and new software should not use it.
or an instruction fetch. This address is then submitted to the MMU
for translation to either a physical memory address or an I/O address.
supervisor-level processing.
Glossary of Terms and Abbreviations
Glossary--3
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