Motorola MPC860 PowerQUICC User Manual page 174

Part II. PowerPC Microprocessor Module
Table 6-24. Translation Lookaside Buffer Management Instructions
Name
TLB Invalidate All
TLB Invalidate Entry
TLB Synchronize
Because the presence and exact semantics of the TLB management instructions is
implementation-dependent, system software should incorporate uses of the instructions
into subroutines to maximize compatibility with programs written for other processors.
6.2.7 Recommended SimpliÞed Mnemonics
To simplify assembly language programs, a set of simplified mnemonics is provided for
some of the most frequently used operations (such as no-op, load immediate, load address,
move register, and complement register). PowerPC compliant assemblers provide the
simplified mnemonics listed in ÒRecommended Simplified MnemonicsÓ in Appendix F,
ÒSimplified Mnemonics,Ó in The Programming Environments Manual and listed with
some of the instruction descriptions in this chapter. Programs written to be portable across
the various assemblers for the PowerPC architecture should not assume the existence of
mnemonics not described in this document.
For a complete list of simpliÞed mnemonics, see Appendix F, ÒSimpliÞed Mnemonics,Ó in
The Programming Environments Manual.
6-24
Mnemonic Syntax
tlbia Ñ
tlbie rB
tlbsync Ñ
MPC860 PowerQUICC UserÕs Manual
MPC860 Notes
Ñ
Ñ
Has no effect. Treated like a no-op.
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