Motorola MPC860 PowerQUICC User Manual page 386

Part IV. Hardware Interface
MPC860
Figure 14-25. Termination Signals Protocol Basic Connection
clkout
a[0Ð31]
r/w
tsiz[0Ð1]
ts
data
ta, bi, tea
Figure 14-26. Termination Signals Protocol Timing Diagram
14.4.9 Memory Reservation
The MPC860 memory reservation protocol supports multilevel bus structures. For each
local bus, reservations are handled by the local reservation logic. The protocol tries to
optimize reservation cancellation such that a PowerPC processor is notiÞed of memory
reservation loss on a remote bus only when it has issued a STWCX cycle to that address.
14-34
External Bus
Acknowledge
Signals
Slave 2
slave 1
Slave 1 Slave 1
allowed to negates
drive acknowledge
acknowledge signals
signals and
Ôturn offÕ
MPC860 PowerQUICC UserÕs Manual
Slave 1
slave 2
Slave 2 Slave 2
allowed to negates
drive acknowledge
acknowledge signals
signals and
Ôturn offÕ
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