Motorola MPC860 PowerQUICC User Manual page 418

Part IV. Hardware Interface
information, see Section 15.5.8, ÒTMIST: Facilitating Nesting of SIU Timer Interrupts.
Note that the RTC, PIT, TB, and DEC operate in deep-sleep mode only if their timing
reference is OSCM. In all other aspects, the behavior of deep-sleep mode is identical to that
of sleep mode.
15.5.7 Power-Down Mode
Power-down mode describes the condition where a power source is applied to KAPWR, but
the power source for VDDH, VDDL, and VDDSYN has been shut down. The behavior in
this mode is similar to deep-sleep mode, in that the SPLL is shut down and only the
real-time clock (RTC), periodic interrupt timer (PIT), timebase (TB), and decrementer
(DEC) are active. The RTC, PIT, TB, and DEC operate in power-down mode only if their
timing reference is OSCM.
Exiting from power-down mode requires a full hardware reset. Note that if it is required that
the PIT, TB, DEC, and SPLL registers and settings not change during power-down mode
and the subsequent reset, then PORESET should be pulled high throughout power-down
mode and HRESET should be used for the reset during wake-up. Otherwise, PORESET can
be used for this reset source. After initial power-up, PORESET assertion does not effect the
RTC registers.
To maintain stability of the crystal oscillator, switchover between the main power supply
and KAPWR supply should be done smoothly. The maximum power supply rise time seen
at the KAPWR pin should be less than 1.7 V/ms for a 32-KHz input frequency.
Power-down mode can be used for:
¥ A software-initiated controlled shutdown, with optional automatic wakeup,
¥ Maintaining integrity of the real-time clock (RTC) during a power failure.
15.5.7.1 Software Initiation of Power-Down Mode, with Automatic
Wake-up
Power-down mode can be initiated in software if the external TEXP signal is used to control
the power supply for VDDH, VDDL, and VDDSYN. If software clears TEXPS, the TEXP
signal will deassert. This signal deassertion can be used externally to shut down the VDDH,
VDDL, and VDDSYN power supplies. In performing this operation, TEXP should be
deasserted by setting PLPRCR[LPM]=11 and clearing PLPRCR[TEXPS] (by writing 1).
The TEXP signal can also be used to enable automatic or externally-initiated wakeup from
power-down mode. When the RTC, PIT, TB, or DEC generate an event, or when HRESET
is asserted externally, PLPRCR[TEXPS] is set and the TEXP pin is asserted. TEXP can be
externally connected to a switch that turns on the power supply to the chip, as illustrated in
Figure 15-14. The MPC860 should then go through a normal hardware reset sequence.
When performing this hardware reset sequence, it is important to allow enough time for the
oscillator to warm up and the SPLL to lock.
15-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA